From patchwork Tue Oct 4 13:54:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 9361921 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 90A5C60752 for ; Tue, 4 Oct 2016 13:55:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 82104287D5 for ; Tue, 4 Oct 2016 13:55:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 76A64287E5; Tue, 4 Oct 2016 13:55:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DBA99287D5 for ; Tue, 4 Oct 2016 13:55:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6BA936E684; Tue, 4 Oct 2016 13:55:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id CEF196E684 for ; Tue, 4 Oct 2016 13:55:04 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP; 04 Oct 2016 06:55:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.31,295,1473145200"; d="scan'208"; a="1049331466" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga001.fm.intel.com with ESMTP; 04 Oct 2016 06:55:03 -0700 Received: from mwiniars-desk1.ger.corp.intel.com (172.28.171.143) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server id 14.3.248.2; Tue, 4 Oct 2016 14:55:02 +0100 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: Date: Tue, 4 Oct 2016 15:54:26 +0200 Message-ID: <1475589267-12440-2-git-send-email-michal.winiarski@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1475589267-12440-1-git-send-email-michal.winiarski@intel.com> References: <1475589267-12440-1-git-send-email-michal.winiarski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.171.143] Cc: Mika Kuoppala Subject: [Intel-gfx] [PATCH 2/3] drm/i915/gtt: Free unused lower-level page tables X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Since "Dynamic page table allocations" were introduced, our page tables can grow (being dynamically allocated) with address space range usage. Unfortunately, their lifetime is bound to vm. This is not a huge problem when we're not using softpin - drm_mm is creating an upper bound on used range by causing addresses for our VMAs to eventually be reused. With softpin, long lived contexts can drain the system out of memory even with a single "small" object. For example: bo = bo_alloc(size); while(true) offset += size; exec(bo, offset); Will cause us to create new allocations until all memory in the system is used for tracking GPU pages (even though almost all PTEs in this vm are pointing to scratch). Let's free unused page tables in clear_range to prevent this - if no entries are used, we can safely free it and return this information to the caller (so that higher-level entry is pointing to scratch). Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Michel Thierry Cc: Mika Kuoppala Signed-off-by: Michał Winiarski --- drivers/gpu/drm/i915/i915_gem_gtt.c | 103 ++++++++++++++++++++++++++++++------ 1 file changed, 88 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 6086122..281e349 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -218,9 +218,10 @@ static gen8_pte_t gen8_pte_encode(dma_addr_t addr, } static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, - const enum i915_cache_level level) + const enum i915_cache_level level, + bool valid) { - gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; + gen8_pde_t pde = valid ? _PAGE_PRESENT | _PAGE_RW : 0; pde |= addr; if (level != I915_CACHE_NONE) pde |= PPAT_CACHED_PDE_INDEX; @@ -532,7 +533,8 @@ static void gen8_initialize_pd(struct i915_address_space *vm, { gen8_pde_t scratch_pde; - scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); + scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC, + true); fill_px(vm->dev, pd, scratch_pde); } @@ -613,7 +615,8 @@ static void gen8_initialize_pdp(struct i915_address_space *vm, { gen8_ppgtt_pdpe_t scratch_pdpe; - scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); + scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC, + true); fill_px(vm->dev, pdp, scratch_pdpe); } @@ -624,7 +627,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm, gen8_ppgtt_pml4e_t scratch_pml4e; scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), - I915_CACHE_LLC); + I915_CACHE_LLC, true); fill_px(vm->dev, pml4, scratch_pml4e); } @@ -641,7 +644,8 @@ gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, return; page_directorypo = kmap_px(pdp); - page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); + page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC, + true); kunmap_px(ppgtt, page_directorypo); } @@ -654,7 +658,7 @@ gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)); - pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); + pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC, true); kunmap_px(ppgtt, pagemap); } @@ -706,7 +710,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); } -static void gen8_ppgtt_clear_pt(struct i915_address_space *vm, +static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, struct i915_page_table *pt, uint64_t start, uint64_t length, @@ -724,50 +728,102 @@ static void gen8_ppgtt_clear_pt(struct i915_address_space *vm, I915_CACHE_LLC, use_scratch); if (WARN_ON(!px_page(pt))) - return; + return false; bitmap_clear(pt->used_ptes, pte_start, num_entries); + if (bitmap_empty(pt->used_ptes, GEN8_PTES)) { + free_pt(vm->dev, pt); + return true; + } + pt_vaddr = kmap_px(pt); for (pte = pte_start; pte < num_entries; pte++) pt_vaddr[pte] = scratch_pte; kunmap_px(ppgtt, pt_vaddr); + + return false; } -static void gen8_ppgtt_clear_pd(struct i915_address_space *vm, +static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, struct i915_page_directory *pd, uint64_t start, uint64_t length, bool use_scratch) { + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct i915_page_table *pt; uint64_t pde; + gen8_pde_t *pde_vaddr; + gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), + I915_CACHE_LLC, use_scratch); + bool reduce; + gen8_for_each_pde(pt, pd, start, length, pde) { if (WARN_ON(!pd->page_table[pde])) break; - gen8_ppgtt_clear_pt(vm, pt, start, length, use_scratch); + reduce = gen8_ppgtt_clear_pt(vm, pt, start, length, + use_scratch); + + if (reduce) { + __clear_bit(pde, pd->used_pdes); + pde_vaddr = kmap_px(pd); + pde_vaddr[pde] = scratch_pde; + kunmap_px(ppgtt, pde_vaddr); + } + } + + if (bitmap_empty(pd->used_pdes, I915_PDES)) { + free_pd(vm->dev, pd); + return true; } + + return false; } -static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm, +static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, struct i915_page_directory_pointer *pdp, uint64_t start, uint64_t length, bool use_scratch) { + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct i915_page_directory *pd; uint64_t pdpe; + gen8_ppgtt_pdpe_t *pdpe_vaddr; + gen8_ppgtt_pdpe_t scratch_pdpe = + gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC, + use_scratch); + bool reduce; + gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { if (WARN_ON(!pdp->page_directory[pdpe])) break; - gen8_ppgtt_clear_pd(vm, pd, start, length, use_scratch); + reduce = gen8_ppgtt_clear_pd(vm, pd, start, length, + use_scratch); + + if (reduce) { + __clear_bit(pdpe, pdp->used_pdpes); + pdpe_vaddr = kmap_px(pdp); + pdpe_vaddr[pdpe] = scratch_pdpe; + kunmap_px(ppgtt, pdpe_vaddr); + } + } + + if (bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(vm->dev))) { + free_pdp(vm->dev, pdp); + return true; } + + return false; } static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, @@ -776,14 +832,30 @@ static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, uint64_t length, bool use_scratch) { + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct i915_page_directory_pointer *pdp; uint64_t pml4e; + gen8_ppgtt_pml4e_t *pml4e_vaddr; + gen8_ppgtt_pml4e_t scratch_pml4e = + gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC, + use_scratch); + bool reduce; + gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { if (WARN_ON(!pml4->pdps[pml4e])) break; - gen8_ppgtt_clear_pdp(vm, pdp, start, length, use_scratch); + reduce = gen8_ppgtt_clear_pdp(vm, pdp, start, length, + use_scratch); + + if (reduce) { + __clear_bit(pml4e, pml4->used_pml4es); + pml4e_vaddr = kmap_px(pml4); + pml4e_vaddr[pml4e] = scratch_pml4e; + kunmap_px(ppgtt, pml4e_vaddr); + } } } @@ -1310,7 +1382,8 @@ static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, /* Map the PDE to the page table */ page_directory[pde] = gen8_pde_encode(px_dma(pt), - I915_CACHE_LLC); + I915_CACHE_LLC, + true); trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, gen8_pte_index(start), gen8_pte_count(start, length),