diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 35f0b7c..d3b5671 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1652,7 +1652,15 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	intel_prepare_dp_ddi_buffers(encoder);
 	intel_ddi_init_dp_buf_reg(encoder);
 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
-	intel_dp_start_link_train(intel_dp);
+	if (!intel_dp_start_link_train(intel_dp)) {
+		DRM_ERROR("Link Training failed at link rate = %d, lane count = %d",
+			  link_rate, lane_count);
+		intel_dp->link_train_failed = true;
+		intel_dp->link_train_failed_link_rate = link_rate;
+		intel_dp->link_train_failed_lane_count = lane_count;
+		/* Schedule a Hotplug Uevent to userspace to start modeset */
+		schedule_work(&dev_priv->i915_modeset_retry_work);
+	}
 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
 		intel_dp_stop_link_train(intel_dp);
 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 610316f..4779742 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -313,6 +313,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	int max_dotclk;
+	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
 
 	max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 
@@ -326,8 +327,22 @@ intel_dp_mode_valid(struct drm_connector *connector,
 		target_clock = fixed_mode->clock;
 	}
 
-	max_link_clock = intel_dp_max_link_rate(intel_dp);
-	max_lanes = intel_dp_max_lane_count(intel_dp);
+	/* Prune the modes based on the link rate that failed */
+	if (intel_dp->link_train_failed_link_rate) {
+		intel_dp->link_rate_index = intel_dp_link_rate_index(intel_dp,
+								     common_rates,
+								     intel_dp->link_train_failed_link_rate);
+		if (intel_dp->link_rate_index > 0) {
+			max_link_clock = common_rates[intel_dp->link_rate_index - 1];
+			max_lanes = intel_dp_max_lane_count(intel_dp);
+		} else
+			/* Here we can lower the lane count, but that is DP 1.3 not 1.2 */
+			DRM_ERROR(" No Valid Mode Supported for this Link");
+	}
+	else {
+		max_link_clock = intel_dp_max_link_rate(intel_dp);
+		max_lanes = intel_dp_max_lane_count(intel_dp);
+	}
 
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);
@@ -1623,6 +1638,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			intel_dp->compliance_test_lane_count = 0;
 		}
 
+	/* Fall back to lower link rate in case of failure in previous modeset */
+	if (intel_dp->link_train_failed_link_rate) {
+		min_lane_count = max_lane_count;
+		min_clock = max_clock = intel_dp->link_rate_index - 1;
+		intel_dp->link_train_failed_link_rate = 0;
+		intel_dp->link_rate_index = -1;
+	}
+
 	DRM_DEBUG_KMS("DP link computation with max lane count %i "
 		      "max bw %d pixel clock %iKHz\n",
 		      max_lane_count, common_rates[max_clock],
@@ -4412,9 +4435,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
 	/* Can't disconnect eDP, but you can close the lid... */
 	if (is_edp(intel_dp))
 		status = edp_detect(intel_dp);
-	else if (intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) {
+	else if (intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING ||
+		 intel_dp->link_train_failed) {
 		status = connector_status_disconnected;
 		intel_dp->compliance_test_type = 0;
+		intel_dp->link_train_failed = false;
 		goto out;
 	}
 	else if (intel_digital_port_connected(to_i915(dev),
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 0048b52..10f81ab 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -310,9 +310,15 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp)
 				DP_TRAINING_PATTERN_DISABLE);
 }
 
-void
+bool
 intel_dp_start_link_train(struct intel_dp *intel_dp)
 {
-	intel_dp_link_training_clock_recovery(intel_dp);
-	intel_dp_link_training_channel_equalization(intel_dp);
+	bool ret;
+
+	if (intel_dp_link_training_clock_recovery(intel_dp)) {
+		ret = intel_dp_link_training_channel_equalization(intel_dp);
+		if (ret)
+			return true;
+	}
+	return false;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 82fc4fe..10335ab 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -882,6 +882,10 @@ struct intel_dp {
 	uint32_t DP;
 	int link_rate;
 	uint8_t lane_count;
+	int link_train_failed_link_rate;
+	uint8_t link_train_failed_lane_count;
+	int link_rate_index;
+	bool link_train_failed;
 	uint8_t sink_count;
 	bool link_mst;
 	bool has_audio;
@@ -1389,7 +1393,7 @@ bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
 			      int link_rate, uint8_t lane_count,
 			      bool link_mst);
-void intel_dp_start_link_train(struct intel_dp *intel_dp);
+bool intel_dp_start_link_train(struct intel_dp *intel_dp);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 void intel_dp_encoder_reset(struct drm_encoder *encoder);
