| Message ID | 1476192112-25336-8-git-send-email-tvrtko.ursulin@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Oct 11, 2016 at 02:21:40PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Saves 4472 bytes of .rodata strings. > > v2: Add parantheses around dev_priv. (Ville Syrjala) Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 14 +++-- > drivers/gpu/drm/i915/i915_drv.h | 111 +++++++++++++++++---------------- > drivers/gpu/drm/i915/i915_gem.c | 36 +++++------ > drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- > drivers/gpu/drm/i915/i915_gem_tiling.c | 3 +- > drivers/gpu/drm/i915/i915_irq.c | 2 +- > drivers/gpu/drm/i915/intel_crt.c | 4 +- > drivers/gpu/drm/i915/intel_display.c | 58 +++++++++-------- > drivers/gpu/drm/i915/intel_dp.c | 2 +- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/intel_i2c.c | 5 +- > drivers/gpu/drm/i915/intel_lvds.c | 9 ++- > drivers/gpu/drm/i915/intel_pm.c | 26 ++++---- > drivers/gpu/drm/i915/intel_sdvo.c | 11 ++-- > drivers/gpu/drm/i915/intel_tv.c | 4 +- > 15 files changed, 151 insertions(+), 142 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index fbb4e2e0d124..bfdbbb745939 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -188,12 +188,14 @@ static void intel_detect_pch(struct drm_device *dev) > dev_priv->pch_type = PCH_LPT; > DRM_DEBUG_KMS("Found LynxPoint PCH\n"); > WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); > - WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); > + WARN_ON(IS_HSW_ULT(dev_priv) || > + IS_BDW_ULT(dev_priv)); > } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { > dev_priv->pch_type = PCH_LPT; > DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); > WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); > - WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); > + WARN_ON(!IS_HSW_ULT(dev_priv) && > + !IS_BDW_ULT(dev_priv)); > } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { > dev_priv->pch_type = PCH_SPT; > DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); > @@ -422,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev) > > dev_priv->mchbar_need_disable = false; > > - if (IS_I915G(dev) || IS_I915GM(dev)) { > + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { > pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); > enabled = !!(temp & DEVEN_MCHBAR_EN); > } else { > @@ -440,7 +442,7 @@ intel_setup_mchbar(struct drm_device *dev) > dev_priv->mchbar_need_disable = true; > > /* Space is allocated or reserved, so enable it. */ > - if (IS_I915G(dev) || IS_I915GM(dev)) { > + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { > pci_write_config_dword(dev_priv->bridge_dev, DEVEN, > temp | DEVEN_MCHBAR_EN); > } else { > @@ -456,7 +458,7 @@ intel_teardown_mchbar(struct drm_device *dev) > int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > > if (dev_priv->mchbar_need_disable) { > - if (IS_I915G(dev) || IS_I915GM(dev)) { > + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { > u32 deven_val; > > pci_read_config_dword(dev_priv->bridge_dev, DEVEN, > @@ -1077,7 +1079,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) > * be lost or delayed, but we use them anyways to avoid > * stuck interrupts on some machines. > */ > - if (!IS_I945G(dev) && !IS_I945GM(dev)) { > + if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) { > if (pci_enable_msi(pdev) < 0) > DRM_DEBUG_DRIVER("can't enable MSI"); > } > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 58045cd7a087..7a40dfa830e7 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2605,7 +2605,8 @@ struct drm_i915_cmd_table { > }) > #define INTEL_INFO(p) (&__I915__(p)->info) > #define INTEL_GEN(p) (INTEL_INFO(p)->gen) > -#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) > + > +#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) > > #define REVID_FOREVER 0xff > #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) > @@ -2637,27 +2638,27 @@ struct drm_i915_cmd_table { > #define IS_REVID(p, since, until) \ > (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) > > -#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) > -#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) > +#define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577) > +#define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562) > #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) > -#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) > +#define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572) > #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) > -#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) > -#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) > +#define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592) > +#define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772) > #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) > #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) > #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) > -#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) > +#define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42) > #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) > -#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) > -#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) > +#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) > +#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) > #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) > #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) > -#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) > +#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) > #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) > -#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ > - INTEL_DEVID(dev) == 0x0152 || \ > - INTEL_DEVID(dev) == 0x015a) > +#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \ > + INTEL_DEVID(dev_priv) == 0x0152 || \ > + INTEL_DEVID(dev_priv) == 0x015a) > #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) > #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) > #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) > @@ -2666,44 +2667,44 @@ struct drm_i915_cmd_table { > #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) > #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) > #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) > -#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ > - (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) > -#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ > - ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ > - (INTEL_DEVID(dev) & 0xf) == 0xb || \ > - (INTEL_DEVID(dev) & 0xf) == 0xe)) > +#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ > + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) We've got a policy for the driver elsewhere that we drop workarounds for pre-release hardware once proper hardware is available. What's so special about this particular piece of hardware that makes the workaround worth keeping around? Anyone? > +#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ > + ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ > + (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ > + (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) > /* ULX machines are also considered ULT. */ > -#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ > - (INTEL_DEVID(dev) & 0xf) == 0xe) > -#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ > - (INTEL_DEVID(dev) & 0x00F0) == 0x0020) > -#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ > - (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) > -#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ > - (INTEL_DEVID(dev) & 0x00F0) == 0x0020) > +#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ > + (INTEL_DEVID(dev_priv) & 0xf) == 0xe) > +#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ > + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) > +#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ > + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) > +#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ > + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) > /* ULX machines are also considered ULT. */ > -#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ > - INTEL_DEVID(dev) == 0x0A1E) > -#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ > - INTEL_DEVID(dev) == 0x1913 || \ > - INTEL_DEVID(dev) == 0x1916 || \ > - INTEL_DEVID(dev) == 0x1921 || \ > - INTEL_DEVID(dev) == 0x1926) > -#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ > - INTEL_DEVID(dev) == 0x1915 || \ > - INTEL_DEVID(dev) == 0x191E) > -#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ > - INTEL_DEVID(dev) == 0x5913 || \ > - INTEL_DEVID(dev) == 0x5916 || \ > - INTEL_DEVID(dev) == 0x5921 || \ > - INTEL_DEVID(dev) == 0x5926) > -#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ > - INTEL_DEVID(dev) == 0x5915 || \ > - INTEL_DEVID(dev) == 0x591E) > -#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ > - (INTEL_DEVID(dev) & 0x00F0) == 0x0020) > -#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ > - (INTEL_DEVID(dev) & 0x00F0) == 0x0030) > +#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ > + INTEL_DEVID(dev_priv) == 0x0A1E) > +#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ > + INTEL_DEVID(dev_priv) == 0x1913 || \ > + INTEL_DEVID(dev_priv) == 0x1916 || \ > + INTEL_DEVID(dev_priv) == 0x1921 || \ > + INTEL_DEVID(dev_priv) == 0x1926) > +#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ > + INTEL_DEVID(dev_priv) == 0x1915 || \ > + INTEL_DEVID(dev_priv) == 0x191E) > +#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ > + INTEL_DEVID(dev_priv) == 0x5913 || \ > + INTEL_DEVID(dev_priv) == 0x5916 || \ > + INTEL_DEVID(dev_priv) == 0x5921 || \ > + INTEL_DEVID(dev_priv) == 0x5926) > +#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ > + INTEL_DEVID(dev_priv) == 0x5915 || \ > + INTEL_DEVID(dev_priv) == 0x591E) > +#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ > + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) > +#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ > + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030) > > #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) > > @@ -2782,7 +2783,7 @@ struct drm_i915_cmd_table { > #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) > > /* Early gen2 have a totally busted CS tlb and require pinned batches. */ > -#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) > +#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv)) > > /* WaRsDisableCoarsePowerGating:skl,bxt */ > #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ > @@ -2802,8 +2803,9 @@ struct drm_i915_cmd_table { > /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte > * rows, which changed the alignment requirements and fence programming. > */ > -#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ > - IS_I915GM(dev))) > +#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ > + !(IS_I915G(dev_priv) || \ > + IS_I915GM(dev_priv))) > #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) > #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) > > @@ -2811,7 +2813,7 @@ struct drm_i915_cmd_table { > #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) > #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) > > -#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) > +#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) > > #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst) > > @@ -2867,7 +2869,8 @@ struct drm_i915_cmd_table { > > /* DPF == dynamic parity feature */ > #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf) > -#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) > +#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ > + 2 : HAS_L3_DPF(dev_priv)) > > #define GT_FREQUENCY_MULTIPLIER 50 > #define GEN9_FREQ_SCALER 3 > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 6b099f0198cc..afaa49946042 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4321,30 +4321,28 @@ void i915_gem_init_swizzling(struct drm_device *dev) > BUG(); > } > > -static void init_unused_ring(struct drm_device *dev, u32 base) > +static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) > { > - struct drm_i915_private *dev_priv = to_i915(dev); > - > I915_WRITE(RING_CTL(base), 0); > I915_WRITE(RING_HEAD(base), 0); > I915_WRITE(RING_TAIL(base), 0); > I915_WRITE(RING_START(base), 0); > } > > -static void init_unused_rings(struct drm_device *dev) > -{ > - if (IS_I830(dev)) { > - init_unused_ring(dev, PRB1_BASE); > - init_unused_ring(dev, SRB0_BASE); > - init_unused_ring(dev, SRB1_BASE); > - init_unused_ring(dev, SRB2_BASE); > - init_unused_ring(dev, SRB3_BASE); > - } else if (IS_GEN2(dev)) { > - init_unused_ring(dev, SRB0_BASE); > - init_unused_ring(dev, SRB1_BASE); > - } else if (IS_GEN3(dev)) { > - init_unused_ring(dev, PRB1_BASE); > - init_unused_ring(dev, PRB2_BASE); > +static void init_unused_rings(struct drm_i915_private *dev_priv) > +{ > + if (IS_I830(dev_priv)) { > + init_unused_ring(dev_priv, PRB1_BASE); > + init_unused_ring(dev_priv, SRB0_BASE); > + init_unused_ring(dev_priv, SRB1_BASE); > + init_unused_ring(dev_priv, SRB2_BASE); > + init_unused_ring(dev_priv, SRB3_BASE); > + } else if (IS_GEN2(dev_priv)) { > + init_unused_ring(dev_priv, SRB0_BASE); > + init_unused_ring(dev_priv, SRB1_BASE); > + } else if (IS_GEN3(dev_priv)) { > + init_unused_ring(dev_priv, PRB1_BASE); > + init_unused_ring(dev_priv, PRB2_BASE); > } > } > > @@ -4362,7 +4360,7 @@ i915_gem_init_hw(struct drm_device *dev) > I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); > > if (IS_HASWELL(dev)) > - I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? > + I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? > LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); > > if (HAS_PCH_NOP(dev_priv)) { > @@ -4385,7 +4383,7 @@ i915_gem_init_hw(struct drm_device *dev) > * will prevent c3 entry. Makes sure all unused rings > * are totally idle. > */ > - init_unused_rings(dev); > + init_unused_rings(dev_priv); > > BUG_ON(!dev_priv->kernel_context); > > diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c > index 59989e8ee5dc..cbea6fb83ce5 100644 > --- a/drivers/gpu/drm/i915/i915_gem_stolen.c > +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c > @@ -115,7 +115,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) > pci_read_config_dword(pdev, INTEL_BSM, &bsm); > > base = bsm & INTEL_BSM_MASK; > - } else if (IS_I865G(dev)) { > + } else if (IS_I865G(dev_priv)) { > u32 tseg_size = 0; > u16 toud = 0; > u8 tmp; > @@ -154,7 +154,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) > tom = tmp * MB(32); > > base = tom - tseg_size - ggtt->stolen_size; > - } else if (IS_845G(dev)) { > + } else if (IS_845G(dev_priv)) { > u32 tseg_size = 0; > u32 tom; > u8 tmp; > @@ -178,7 +178,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) > tom = tmp * MB(32); > > base = tom - tseg_size - ggtt->stolen_size; > - } else if (IS_I830(dev)) { > + } else if (IS_I830(dev_priv)) { > u32 tseg_size = 0; > u32 tom; > u8 tmp; > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c > index a14b1e3d4c78..89d1d234a1b4 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -62,6 +62,7 @@ > static bool > i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) > { > + struct drm_i915_private *dev_priv = to_i915(dev); > int tile_width; > > /* Linear is always fine */ > @@ -72,7 +73,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) > return false; > > if (IS_GEN2(dev) || > - (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) > + (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv))) > tile_width = 128; > else > tile_width = 512; > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 883474411aee..5fb3b1c9a52c 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3656,7 +3656,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) > > ibx_irq_postinstall(dev); > > - if (IS_IRONLAKE_M(dev)) { > + if (IS_IRONLAKE_M(dev_priv)) { > /* Enable PCU event interrupts > * > * spinlocking not required here for correctness since interrupt > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index f8919ef3a7af..d4388c03b4da 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -431,7 +431,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) > * to get a reliable result. > */ > > - if (IS_G4X(dev) && !IS_GM45(dev)) > + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) > tries = 2; > else > tries = 1; > @@ -894,7 +894,7 @@ void intel_crt_init(struct drm_device *dev) > > crt->base.type = INTEL_OUTPUT_ANALOG; > crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); > - if (IS_I830(dev)) > + if (IS_I830(dev_priv)) > crt->base.crtc_mask = (1 << 0); > else > crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index b7685936d324..ee3b593d3ec2 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1230,10 +1230,9 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) > static void assert_cursor(struct drm_i915_private *dev_priv, > enum pipe pipe, bool state) > { > - struct drm_device *dev = &dev_priv->drm; > bool cur_state; > > - if (IS_845G(dev) || IS_I865G(dev)) > + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) > cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; > else > cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; > @@ -1617,11 +1616,11 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) > assert_pipe_disabled(dev_priv, crtc->pipe); > > /* PLL is protected by panel, make sure we can write it */ > - if (IS_MOBILE(dev) && !IS_I830(dev)) > + if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) > assert_panel_unlocked(dev_priv, crtc->pipe); > > /* Enable DVO 2x clock on both PLLs if necessary */ > - if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { > + if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) { > /* > * It appears to be important that we don't enable this > * for the current pipe before otherwise configuring the > @@ -1686,7 +1685,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc) > enum pipe pipe = crtc->pipe; > > /* Disable DVO 2x clock on both PLLs if necessary */ > - if (IS_I830(dev) && > + if (IS_I830(dev_priv) && > intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && > !intel_num_dvo_pipes(dev)) { > I915_WRITE(DPLL(PIPE_B), > @@ -5392,7 +5391,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, > /* IPS only exists on ULT machines and is tied to pipe A. */ > static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) > { > - return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; > + return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; > } > > static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > @@ -5864,9 +5863,9 @@ static void intel_update_max_cdclk(struct drm_device *dev) > */ > if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) > dev_priv->max_cdclk_freq = 450000; > - else if (IS_BDW_ULX(dev)) > + else if (IS_BDW_ULX(dev_priv)) > dev_priv->max_cdclk_freq = 450000; > - else if (IS_BDW_ULT(dev)) > + else if (IS_BDW_ULT(dev_priv)) > dev_priv->max_cdclk_freq = 540000; > else > dev_priv->max_cdclk_freq = 675000; > @@ -7225,7 +7224,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) > return -EINVAL; > > - if (HAS_IPS(dev)) > + if (HAS_IPS(dev_priv)) > hsw_compute_ips_config(crtc, pipe_config); > > if (pipe_config->has_pch_encoder) > @@ -7363,7 +7362,7 @@ static int haswell_get_display_clock_speed(struct drm_device *dev) > return 450000; > else if (freq == LCPLL_CLK_FREQ_450) > return 450000; > - else if (IS_HSW_ULT(dev)) > + else if (IS_HSW_ULT(dev_priv)) > return 337500; > else > return 540000; > @@ -7533,7 +7532,7 @@ static unsigned int intel_hpll_vco(struct drm_device *dev) > uint8_t tmp = 0; > > /* FIXME other chipsets? */ > - if (IS_GM45(dev)) > + if (IS_GM45(dev_priv)) > vco_table = ctg_vco; > else if (IS_G4X(dev)) > vco_table = elk_vco; > @@ -8152,7 +8151,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, > else > dpll |= DPLLB_MODE_DAC_SERIAL; > > - if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { > + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) { > dpll |= (crtc_state->pixel_multiplier - 1) > << SDVO_MULTIPLIER_SHIFT_HIRES; > } > @@ -8231,7 +8230,8 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc, > dpll |= PLL_P2_DIVIDE_BY_4; > } > > - if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) > + if (!IS_I830(dev_priv) && > + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) > dpll |= DPLL_DVO_2X_MODE; > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && > @@ -8654,7 +8654,8 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, > struct drm_i915_private *dev_priv = to_i915(dev); > uint32_t tmp; > > - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) > + if (INTEL_GEN(dev_priv) <= 3 && > + (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) > return; > > tmp = I915_READ(PFIT_CONTROL); > @@ -8864,7 +8865,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) > >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; > pipe_config->dpll_hw_state.dpll_md = tmp; > - } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { > + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || > + IS_G33(dev_priv)) { > tmp = I915_READ(DPLL(crtc->pipe)); > pipe_config->pixel_multiplier = > ((tmp & SDVO_MULTIPLIER_MASK) > @@ -8882,7 +8884,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > * on 830. Filter it out here so that we don't > * report errors due to that. > */ > - if (IS_I830(dev)) > + if (IS_I830(dev_priv)) > pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; > > pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); > @@ -10904,13 +10906,13 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, > > I915_WRITE(CURPOS(pipe), pos); > > - if (IS_845G(dev) || IS_I865G(dev)) > + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) > i845_update_cursor(crtc, base, plane_state); > else > i9xx_update_cursor(crtc, base, plane_state); > } > > -static bool cursor_size_ok(struct drm_device *dev, > +static bool cursor_size_ok(struct drm_i915_private *dev_priv, > uint32_t width, uint32_t height) > { > if (width == 0 || height == 0) > @@ -10922,11 +10924,11 @@ static bool cursor_size_ok(struct drm_device *dev, > * the precision of the register. Everything else requires > * square cursors, limited to a few power-of-two sizes. > */ > - if (IS_845G(dev) || IS_I865G(dev)) { > + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { > if ((width & 63) != 0) > return false; > > - if (width > (IS_845G(dev) ? 64 : 512)) > + if (width > (IS_845G(dev_priv) ? 64 : 512)) > return false; > > if (height > 1023) > @@ -10935,7 +10937,7 @@ static bool cursor_size_ok(struct drm_device *dev, > switch (width | height) { > case 256: > case 128: > - if (IS_GEN2(dev)) > + if (IS_GEN2(dev_priv)) > return false; > case 64: > break; > @@ -11377,7 +11379,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, > else > port_clock = i9xx_calc_dpll_params(refclk, &clock); > } else { > - u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); > + u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); > bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); > > if (is_lvds) { > @@ -14658,6 +14660,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, > struct drm_plane_state *new_state) > { > struct drm_device *dev = plane->dev; > + struct drm_i915_private *dev_priv = to_i915(dev); > struct drm_framebuffer *fb = new_state->fb; > struct drm_i915_gem_object *obj = intel_fb_obj(fb); > struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); > @@ -14709,7 +14712,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, > > if (plane->type == DRM_PLANE_TYPE_CURSOR && > INTEL_INFO(dev)->cursor_needs_physical) { > - int align = IS_I830(dev) ? 16 * 1024 : 256; > + int align = IS_I830(dev_priv) ? 16 * 1024 : 256; > ret = i915_gem_object_attach_phys(obj, align); > if (ret) > DRM_DEBUG_KMS("failed to attach phys object\n"); > @@ -15031,7 +15034,8 @@ intel_check_cursor_plane(struct drm_plane *plane, > return 0; > > /* Check for which cursor types we support */ > - if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { > + if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, > + state->base.crtc_h)) { > DRM_DEBUG("Cursor dimension %dx%d not supported\n", > state->base.crtc_w, state->base.crtc_h); > return -EINVAL; > @@ -15325,7 +15329,7 @@ static bool intel_crt_present(struct drm_device *dev) > if (INTEL_INFO(dev)->gen >= 9) > return false; > > - if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) > + if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) > return false; > > if (IS_CHERRYVIEW(dev)) > @@ -16384,8 +16388,8 @@ void intel_modeset_init(struct drm_device *dev) > dev->mode_config.max_height = 8192; > } > > - if (IS_845G(dev) || IS_I865G(dev)) { > - dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; > + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { > + dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512; > dev->mode_config.cursor_height = 1023; > } else if (IS_GEN2(dev)) { > dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 51d92a9c6cb1..2e06dfb64bd4 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -5748,7 +5748,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > * 0xd. Failure to do so will result in spurious interrupts being > * generated on the port when a cable is not attached. > */ > - if (IS_G4X(dev) && !IS_GM45(dev)) { > + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { > u32 temp = I915_READ(PEG_BAND_GAP_DATA); > I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); > } > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index ad3ff4fe63cf..6607c4e3c36c 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1921,7 +1921,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, > * 0xd. Failure to do so will result in spurious interrupts being > * generated on the port when a cable is not attached. > */ > - if (IS_G4X(dev) && !IS_GM45(dev)) { > + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { > u32 temp = I915_READ(PEG_BAND_GAP_DATA); > I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); > } > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > index 1410330ec9bb..afb2652919d0 100644 > --- a/drivers/gpu/drm/i915/intel_i2c.c > +++ b/drivers/gpu/drm/i915/intel_i2c.c > @@ -138,11 +138,10 @@ static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) > static u32 get_reserved(struct intel_gmbus *bus) > { > struct drm_i915_private *dev_priv = bus->dev_priv; > - struct drm_device *dev = &dev_priv->drm; > u32 reserved = 0; > > /* On most chips, these bits must be preserved in software. */ > - if (!IS_I830(dev) && !IS_845G(dev)) > + if (!IS_I830(dev_priv) && !IS_845G(dev_priv)) > reserved = I915_READ_NOTRACE(bus->gpio_reg) & > (GPIO_DATA_PULLUP_DISABLE | > GPIO_CLOCK_PULLUP_DISABLE); > @@ -674,7 +673,7 @@ int intel_setup_gmbus(struct drm_device *dev) > bus->reg0 = pin | GMBUS_RATE_100KHZ; > > /* gmbus seems to be broken on i830 */ > - if (IS_I830(dev)) > + if (IS_I830(dev_priv)) > bus->force_bit = 1; > > intel_gpio_setup(bus, pin); > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c > index baaf2ed897ef..1c47f99917e6 100644 > --- a/drivers/gpu/drm/i915/intel_lvds.c > +++ b/drivers/gpu/drm/i915/intel_lvds.c > @@ -949,10 +949,8 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) > return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; > } > > -static bool intel_lvds_supported(struct drm_device *dev) > +static bool intel_lvds_supported(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = to_i915(dev); > - > /* With the introduction of the PCH we gained a dedicated > * LVDS presence pin, use it. */ > if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) > @@ -960,7 +958,8 @@ static bool intel_lvds_supported(struct drm_device *dev) > > /* Otherwise LVDS was only attached to mobile products, > * except for the inglorious 830gm */ > - if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > + if (INTEL_GEN(dev_priv) <= 4 && > + IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) > return true; > > return false; > @@ -992,7 +991,7 @@ void intel_lvds_init(struct drm_device *dev) > int pipe; > u8 pin; > > - if (!intel_lvds_supported(dev)) > + if (!intel_lvds_supported(dev_priv)) > return; > > /* Skip init on machines we know falsely report LVDS */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 86051ef2716e..04a38a37af2e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -334,12 +334,12 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) > val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; > I915_WRITE(DSPFW3, val); > POSTING_READ(DSPFW3); > - } else if (IS_I945G(dev) || IS_I945GM(dev)) { > + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { > val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : > _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); > I915_WRITE(FW_BLC_SELF, val); > POSTING_READ(FW_BLC_SELF); > - } else if (IS_I915GM(dev)) { > + } else if (IS_I915GM(dev_priv)) { > /* > * FIXME can't find a bit like this for 915G, and > * and yet it does have the related watermark in > @@ -648,8 +648,10 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) > u32 reg; > unsigned long wm; > > - latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, > - dev_priv->fsb_freq, dev_priv->mem_freq); > + latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), > + dev_priv->is_ddr3, > + dev_priv->fsb_freq, > + dev_priv->mem_freq); > if (!latency) { > DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); > intel_set_memory_cxsr(dev_priv, false); > @@ -1579,7 +1581,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) > > DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); > > - if (IS_I915GM(dev) && enabled) { > + if (IS_I915GM(dev_priv) && enabled) { > struct drm_i915_gem_object *obj; > > obj = intel_fb_obj(enabled->primary->state->fb); > @@ -1609,7 +1611,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) > unsigned long line_time_us; > int entries; > > - if (IS_I915GM(dev) || IS_I945GM(dev)) > + if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) > cpp = 4; > > line_time_us = max(htotal * 1000 / clock, 1); > @@ -1623,7 +1625,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) > if (srwm < 0) > srwm = 1; > > - if (IS_I945G(dev) || IS_I945GM(dev)) > + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) > I915_WRITE(FW_BLC_SELF, > FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); > else > @@ -6930,7 +6932,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) > * The bit 22 of 0x42004 > * The bit 7,8,9 of 0x42020. > */ > - if (IS_IRONLAKE_M(dev)) { > + if (IS_IRONLAKE_M(dev_priv)) { > /* WaFbcAsynchFlipDisableFbcQueue:ilk */ > I915_WRITE(ILK_DISPLAY_CHICKEN1, > I915_READ(ILK_DISPLAY_CHICKEN1) | > @@ -7340,7 +7342,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > /* WaDisablePSDDualDispatchEnable:ivb */ > - if (IS_IVB_GT1(dev)) > + if (IS_IVB_GT1(dev_priv)) > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > > @@ -7356,7 +7358,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > GEN7_WA_FOR_GEN7_L3_CONTROL); > I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, > GEN7_WA_L3_CHICKEN_MODE); > - if (IS_IVB_GT1(dev)) > + if (IS_IVB_GT1(dev_priv)) > I915_WRITE(GEN7_ROW_CHICKEN2, > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > else { > @@ -7550,7 +7552,7 @@ static void g4x_init_clock_gating(struct drm_device *dev) > dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | > OVRUNIT_CLOCK_GATE_DISABLE | > OVCUNIT_CLOCK_GATE_DISABLE; > - if (IS_GM45(dev)) > + if (IS_GM45(dev_priv)) > dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; > I915_WRITE(DSPCLK_GATE_D, dspclk_gate); > > @@ -7757,7 +7759,7 @@ void intel_init_pm(struct drm_device *dev) > vlv_setup_wm_latency(dev); > dev_priv->display.update_wm = vlv_update_wm; > } else if (IS_PINEVIEW(dev)) { > - if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), > + if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), > dev_priv->is_ddr3, > dev_priv->fsb_freq, > dev_priv->mem_freq)) { > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c > index 0d9114f9ce27..5fe423571a7e 100644 > --- a/drivers/gpu/drm/i915/intel_sdvo.c > +++ b/drivers/gpu/drm/i915/intel_sdvo.c > @@ -1296,7 +1296,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, > > if (INTEL_INFO(dev)->gen >= 4) { > /* done in crtc_mode_set as the dpll_md reg must be written early */ > - } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { > + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || > + IS_G33(dev_priv)) { > /* done in crtc_mode_set as it lives inside the dpll register */ > } else { > sdvox |= (crtc_state->pixel_multiplier - 1) > @@ -1389,7 +1390,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, > * encoder->get_config we so already have a valid pixel multplier on all > * other platfroms. > */ > - if (IS_I915G(dev) || IS_I915GM(dev)) { > + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { > pipe_config->pixel_multiplier = > ((sdvox & SDVO_PORT_MULTIPLY_MASK) > >> SDVO_PORT_MULTIPLY_SHIFT) + 1; > @@ -1595,15 +1596,15 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in > > static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) > { > - struct drm_device *dev = intel_sdvo->base.base.dev; > + struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); > uint16_t hotplug; > > - if (!I915_HAS_HOTPLUG(dev)) > + if (!I915_HAS_HOTPLUG(dev_priv)) > return 0; > > /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise > * on the line. */ > - if (IS_I945G(dev) || IS_I945GM(dev)) > + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) > return 0; > > if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, > diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c > index 3988c45f9e5f..df16b1dc4c2d 100644 > --- a/drivers/gpu/drm/i915/intel_tv.c > +++ b/drivers/gpu/drm/i915/intel_tv.c > @@ -1095,7 +1095,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, > tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT; > > /* Enable two fixes for the chips that need them. */ > - if (IS_I915GM(dev)) > + if (IS_I915GM(dev_priv)) > tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX; > > set_tv_mode_timings(dev_priv, tv_mode, burst_ena); > @@ -1220,7 +1220,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv, > * The TV sense state should be cleared to zero on cantiga platform. Otherwise > * the TV is misdetected. This is hardware requirement. > */ > - if (IS_GM45(dev)) > + if (IS_GM45(dev_priv)) > tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | > TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL); > > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index fbb4e2e0d124..bfdbbb745939 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -188,12 +188,14 @@ static void intel_detect_pch(struct drm_device *dev) dev_priv->pch_type = PCH_LPT; DRM_DEBUG_KMS("Found LynxPoint PCH\n"); WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); - WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); + WARN_ON(IS_HSW_ULT(dev_priv) || + IS_BDW_ULT(dev_priv)); } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_LPT; DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); - WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); + WARN_ON(!IS_HSW_ULT(dev_priv) && + !IS_BDW_ULT(dev_priv)); } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_SPT; DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); @@ -422,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev) dev_priv->mchbar_need_disable = false; - if (IS_I915G(dev) || IS_I915GM(dev)) { + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); enabled = !!(temp & DEVEN_MCHBAR_EN); } else { @@ -440,7 +442,7 @@ intel_setup_mchbar(struct drm_device *dev) dev_priv->mchbar_need_disable = true; /* Space is allocated or reserved, so enable it. */ - if (IS_I915G(dev) || IS_I915GM(dev)) { + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { pci_write_config_dword(dev_priv->bridge_dev, DEVEN, temp | DEVEN_MCHBAR_EN); } else { @@ -456,7 +458,7 @@ intel_teardown_mchbar(struct drm_device *dev) int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; if (dev_priv->mchbar_need_disable) { - if (IS_I915G(dev) || IS_I915GM(dev)) { + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { u32 deven_val; pci_read_config_dword(dev_priv->bridge_dev, DEVEN, @@ -1077,7 +1079,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) * be lost or delayed, but we use them anyways to avoid * stuck interrupts on some machines. */ - if (!IS_I945G(dev) && !IS_I945GM(dev)) { + if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) { if (pci_enable_msi(pdev) < 0) DRM_DEBUG_DRIVER("can't enable MSI"); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 58045cd7a087..7a40dfa830e7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2605,7 +2605,8 @@ struct drm_i915_cmd_table { }) #define INTEL_INFO(p) (&__I915__(p)->info) #define INTEL_GEN(p) (INTEL_INFO(p)->gen) -#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) + +#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) #define REVID_FOREVER 0xff #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) @@ -2637,27 +2638,27 @@ struct drm_i915_cmd_table { #define IS_REVID(p, since, until) \ (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) -#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) -#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) +#define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577) +#define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562) #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) -#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) +#define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572) #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) -#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) -#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) +#define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592) +#define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772) #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) -#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) +#define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42) #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) -#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) -#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) +#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) +#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) -#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) +#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) -#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ - INTEL_DEVID(dev) == 0x0152 || \ - INTEL_DEVID(dev) == 0x015a) +#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \ + INTEL_DEVID(dev_priv) == 0x0152 || \ + INTEL_DEVID(dev_priv) == 0x015a) #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) @@ -2666,44 +2667,44 @@ struct drm_i915_cmd_table { #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) -#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ - (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) -#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ - ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ - (INTEL_DEVID(dev) & 0xf) == 0xb || \ - (INTEL_DEVID(dev) & 0xf) == 0xe)) +#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) +#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ + ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ + (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ + (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) /* ULX machines are also considered ULT. */ -#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ - (INTEL_DEVID(dev) & 0xf) == 0xe) -#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ - (INTEL_DEVID(dev) & 0x00F0) == 0x0020) -#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ - (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) -#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ - (INTEL_DEVID(dev) & 0x00F0) == 0x0020) +#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0xf) == 0xe) +#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) +#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) +#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) /* ULX machines are also considered ULT. */ -#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ - INTEL_DEVID(dev) == 0x0A1E) -#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ - INTEL_DEVID(dev) == 0x1913 || \ - INTEL_DEVID(dev) == 0x1916 || \ - INTEL_DEVID(dev) == 0x1921 || \ - INTEL_DEVID(dev) == 0x1926) -#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ - INTEL_DEVID(dev) == 0x1915 || \ - INTEL_DEVID(dev) == 0x191E) -#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ - INTEL_DEVID(dev) == 0x5913 || \ - INTEL_DEVID(dev) == 0x5916 || \ - INTEL_DEVID(dev) == 0x5921 || \ - INTEL_DEVID(dev) == 0x5926) -#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ - INTEL_DEVID(dev) == 0x5915 || \ - INTEL_DEVID(dev) == 0x591E) -#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ - (INTEL_DEVID(dev) & 0x00F0) == 0x0020) -#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ - (INTEL_DEVID(dev) & 0x00F0) == 0x0030) +#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ + INTEL_DEVID(dev_priv) == 0x0A1E) +#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ + INTEL_DEVID(dev_priv) == 0x1913 || \ + INTEL_DEVID(dev_priv) == 0x1916 || \ + INTEL_DEVID(dev_priv) == 0x1921 || \ + INTEL_DEVID(dev_priv) == 0x1926) +#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ + INTEL_DEVID(dev_priv) == 0x1915 || \ + INTEL_DEVID(dev_priv) == 0x191E) +#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ + INTEL_DEVID(dev_priv) == 0x5913 || \ + INTEL_DEVID(dev_priv) == 0x5916 || \ + INTEL_DEVID(dev_priv) == 0x5921 || \ + INTEL_DEVID(dev_priv) == 0x5926) +#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ + INTEL_DEVID(dev_priv) == 0x5915 || \ + INTEL_DEVID(dev_priv) == 0x591E) +#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) +#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030) #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) @@ -2782,7 +2783,7 @@ struct drm_i915_cmd_table { #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) /* Early gen2 have a totally busted CS tlb and require pinned batches. */ -#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) +#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv)) /* WaRsDisableCoarsePowerGating:skl,bxt */ #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ @@ -2802,8 +2803,9 @@ struct drm_i915_cmd_table { /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. */ -#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ - IS_I915GM(dev))) +#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ + !(IS_I915G(dev_priv) || \ + IS_I915GM(dev_priv))) #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) @@ -2811,7 +2813,7 @@ struct drm_i915_cmd_table { #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) -#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) +#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst) @@ -2867,7 +2869,8 @@ struct drm_i915_cmd_table { /* DPF == dynamic parity feature */ #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf) -#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) +#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ + 2 : HAS_L3_DPF(dev_priv)) #define GT_FREQUENCY_MULTIPLIER 50 #define GEN9_FREQ_SCALER 3 diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6b099f0198cc..afaa49946042 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4321,30 +4321,28 @@ void i915_gem_init_swizzling(struct drm_device *dev) BUG(); } -static void init_unused_ring(struct drm_device *dev, u32 base) +static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) { - struct drm_i915_private *dev_priv = to_i915(dev); - I915_WRITE(RING_CTL(base), 0); I915_WRITE(RING_HEAD(base), 0); I915_WRITE(RING_TAIL(base), 0); I915_WRITE(RING_START(base), 0); } -static void init_unused_rings(struct drm_device *dev) -{ - if (IS_I830(dev)) { - init_unused_ring(dev, PRB1_BASE); - init_unused_ring(dev, SRB0_BASE); - init_unused_ring(dev, SRB1_BASE); - init_unused_ring(dev, SRB2_BASE); - init_unused_ring(dev, SRB3_BASE); - } else if (IS_GEN2(dev)) { - init_unused_ring(dev, SRB0_BASE); - init_unused_ring(dev, SRB1_BASE); - } else if (IS_GEN3(dev)) { - init_unused_ring(dev, PRB1_BASE); - init_unused_ring(dev, PRB2_BASE); +static void init_unused_rings(struct drm_i915_private *dev_priv) +{ + if (IS_I830(dev_priv)) { + init_unused_ring(dev_priv, PRB1_BASE); + init_unused_ring(dev_priv, SRB0_BASE); + init_unused_ring(dev_priv, SRB1_BASE); + init_unused_ring(dev_priv, SRB2_BASE); + init_unused_ring(dev_priv, SRB3_BASE); + } else if (IS_GEN2(dev_priv)) { + init_unused_ring(dev_priv, SRB0_BASE); + init_unused_ring(dev_priv, SRB1_BASE); + } else if (IS_GEN3(dev_priv)) { + init_unused_ring(dev_priv, PRB1_BASE); + init_unused_ring(dev_priv, PRB2_BASE); } } @@ -4362,7 +4360,7 @@ i915_gem_init_hw(struct drm_device *dev) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); if (IS_HASWELL(dev)) - I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? + I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); if (HAS_PCH_NOP(dev_priv)) { @@ -4385,7 +4383,7 @@ i915_gem_init_hw(struct drm_device *dev) * will prevent c3 entry. Makes sure all unused rings * are totally idle. */ - init_unused_rings(dev); + init_unused_rings(dev_priv); BUG_ON(!dev_priv->kernel_context); diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index 59989e8ee5dc..cbea6fb83ce5 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -115,7 +115,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) pci_read_config_dword(pdev, INTEL_BSM, &bsm); base = bsm & INTEL_BSM_MASK; - } else if (IS_I865G(dev)) { + } else if (IS_I865G(dev_priv)) { u32 tseg_size = 0; u16 toud = 0; u8 tmp; @@ -154,7 +154,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) tom = tmp * MB(32); base = tom - tseg_size - ggtt->stolen_size; - } else if (IS_845G(dev)) { + } else if (IS_845G(dev_priv)) { u32 tseg_size = 0; u32 tom; u8 tmp; @@ -178,7 +178,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) tom = tmp * MB(32); base = tom - tseg_size - ggtt->stolen_size; - } else if (IS_I830(dev)) { + } else if (IS_I830(dev_priv)) { u32 tseg_size = 0; u32 tom; u8 tmp; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index a14b1e3d4c78..89d1d234a1b4 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -62,6 +62,7 @@ static bool i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) { + struct drm_i915_private *dev_priv = to_i915(dev); int tile_width; /* Linear is always fine */ @@ -72,7 +73,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) return false; if (IS_GEN2(dev) || - (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) + (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv))) tile_width = 128; else tile_width = 512; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 883474411aee..5fb3b1c9a52c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3656,7 +3656,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) ibx_irq_postinstall(dev); - if (IS_IRONLAKE_M(dev)) { + if (IS_IRONLAKE_M(dev_priv)) { /* Enable PCU event interrupts * * spinlocking not required here for correctness since interrupt diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index f8919ef3a7af..d4388c03b4da 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -431,7 +431,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) * to get a reliable result. */ - if (IS_G4X(dev) && !IS_GM45(dev)) + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) tries = 2; else tries = 1; @@ -894,7 +894,7 @@ void intel_crt_init(struct drm_device *dev) crt->base.type = INTEL_OUTPUT_ANALOG; crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); - if (IS_I830(dev)) + if (IS_I830(dev_priv)) crt->base.crtc_mask = (1 << 0); else crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b7685936d324..ee3b593d3ec2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1230,10 +1230,9 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) static void assert_cursor(struct drm_i915_private *dev_priv, enum pipe pipe, bool state) { - struct drm_device *dev = &dev_priv->drm; bool cur_state; - if (IS_845G(dev) || IS_I865G(dev)) + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; else cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; @@ -1617,11 +1616,11 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) assert_pipe_disabled(dev_priv, crtc->pipe); /* PLL is protected by panel, make sure we can write it */ - if (IS_MOBILE(dev) && !IS_I830(dev)) + if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) assert_panel_unlocked(dev_priv, crtc->pipe); /* Enable DVO 2x clock on both PLLs if necessary */ - if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { + if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) { /* * It appears to be important that we don't enable this * for the current pipe before otherwise configuring the @@ -1686,7 +1685,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc) enum pipe pipe = crtc->pipe; /* Disable DVO 2x clock on both PLLs if necessary */ - if (IS_I830(dev) && + if (IS_I830(dev_priv) && intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && !intel_num_dvo_pipes(dev)) { I915_WRITE(DPLL(PIPE_B), @@ -5392,7 +5391,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, /* IPS only exists on ULT machines and is tied to pipe A. */ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) { - return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; + return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; } static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, @@ -5864,9 +5863,9 @@ static void intel_update_max_cdclk(struct drm_device *dev) */ if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) dev_priv->max_cdclk_freq = 450000; - else if (IS_BDW_ULX(dev)) + else if (IS_BDW_ULX(dev_priv)) dev_priv->max_cdclk_freq = 450000; - else if (IS_BDW_ULT(dev)) + else if (IS_BDW_ULT(dev_priv)) dev_priv->max_cdclk_freq = 540000; else dev_priv->max_cdclk_freq = 675000; @@ -7225,7 +7224,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) return -EINVAL; - if (HAS_IPS(dev)) + if (HAS_IPS(dev_priv)) hsw_compute_ips_config(crtc, pipe_config); if (pipe_config->has_pch_encoder) @@ -7363,7 +7362,7 @@ static int haswell_get_display_clock_speed(struct drm_device *dev) return 450000; else if (freq == LCPLL_CLK_FREQ_450) return 450000; - else if (IS_HSW_ULT(dev)) + else if (IS_HSW_ULT(dev_priv)) return 337500; else return 540000; @@ -7533,7 +7532,7 @@ static unsigned int intel_hpll_vco(struct drm_device *dev) uint8_t tmp = 0; /* FIXME other chipsets? */ - if (IS_GM45(dev)) + if (IS_GM45(dev_priv)) vco_table = ctg_vco; else if (IS_G4X(dev)) vco_table = elk_vco; @@ -8152,7 +8151,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, else dpll |= DPLLB_MODE_DAC_SERIAL; - if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) { dpll |= (crtc_state->pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; } @@ -8231,7 +8230,8 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc, dpll |= PLL_P2_DIVIDE_BY_4; } - if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) + if (!IS_I830(dev_priv) && + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) dpll |= DPLL_DVO_2X_MODE; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && @@ -8654,7 +8654,8 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(dev); uint32_t tmp; - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) + if (INTEL_GEN(dev_priv) <= 3 && + (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) return; tmp = I915_READ(PFIT_CONTROL); @@ -8864,7 +8865,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; pipe_config->dpll_hw_state.dpll_md = tmp; - } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || + IS_G33(dev_priv)) { tmp = I915_READ(DPLL(crtc->pipe)); pipe_config->pixel_multiplier = ((tmp & SDVO_MULTIPLIER_MASK) @@ -8882,7 +8884,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, * on 830. Filter it out here so that we don't * report errors due to that. */ - if (IS_I830(dev)) + if (IS_I830(dev_priv)) pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); @@ -10904,13 +10906,13 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, I915_WRITE(CURPOS(pipe), pos); - if (IS_845G(dev) || IS_I865G(dev)) + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) i845_update_cursor(crtc, base, plane_state); else i9xx_update_cursor(crtc, base, plane_state); } -static bool cursor_size_ok(struct drm_device *dev, +static bool cursor_size_ok(struct drm_i915_private *dev_priv, uint32_t width, uint32_t height) { if (width == 0 || height == 0) @@ -10922,11 +10924,11 @@ static bool cursor_size_ok(struct drm_device *dev, * the precision of the register. Everything else requires * square cursors, limited to a few power-of-two sizes. */ - if (IS_845G(dev) || IS_I865G(dev)) { + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { if ((width & 63) != 0) return false; - if (width > (IS_845G(dev) ? 64 : 512)) + if (width > (IS_845G(dev_priv) ? 64 : 512)) return false; if (height > 1023) @@ -10935,7 +10937,7 @@ static bool cursor_size_ok(struct drm_device *dev, switch (width | height) { case 256: case 128: - if (IS_GEN2(dev)) + if (IS_GEN2(dev_priv)) return false; case 64: break; @@ -11377,7 +11379,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, else port_clock = i9xx_calc_dpll_params(refclk, &clock); } else { - u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); + u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); if (is_lvds) { @@ -14658,6 +14660,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, struct drm_plane_state *new_state) { struct drm_device *dev = plane->dev; + struct drm_i915_private *dev_priv = to_i915(dev); struct drm_framebuffer *fb = new_state->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); @@ -14709,7 +14712,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, if (plane->type == DRM_PLANE_TYPE_CURSOR && INTEL_INFO(dev)->cursor_needs_physical) { - int align = IS_I830(dev) ? 16 * 1024 : 256; + int align = IS_I830(dev_priv) ? 16 * 1024 : 256; ret = i915_gem_object_attach_phys(obj, align); if (ret) DRM_DEBUG_KMS("failed to attach phys object\n"); @@ -15031,7 +15034,8 @@ intel_check_cursor_plane(struct drm_plane *plane, return 0; /* Check for which cursor types we support */ - if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { + if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, + state->base.crtc_h)) { DRM_DEBUG("Cursor dimension %dx%d not supported\n", state->base.crtc_w, state->base.crtc_h); return -EINVAL; @@ -15325,7 +15329,7 @@ static bool intel_crt_present(struct drm_device *dev) if (INTEL_INFO(dev)->gen >= 9) return false; - if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) + if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) return false; if (IS_CHERRYVIEW(dev)) @@ -16384,8 +16388,8 @@ void intel_modeset_init(struct drm_device *dev) dev->mode_config.max_height = 8192; } - if (IS_845G(dev) || IS_I865G(dev)) { - dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { + dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512; dev->mode_config.cursor_height = 1023; } else if (IS_GEN2(dev)) { dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 51d92a9c6cb1..2e06dfb64bd4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5748,7 +5748,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, * 0xd. Failure to do so will result in spurious interrupts being * generated on the port when a cable is not attached. */ - if (IS_G4X(dev) && !IS_GM45(dev)) { + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { u32 temp = I915_READ(PEG_BAND_GAP_DATA); I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); } diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index ad3ff4fe63cf..6607c4e3c36c 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1921,7 +1921,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, * 0xd. Failure to do so will result in spurious interrupts being * generated on the port when a cable is not attached. */ - if (IS_G4X(dev) && !IS_GM45(dev)) { + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { u32 temp = I915_READ(PEG_BAND_GAP_DATA); I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); } diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 1410330ec9bb..afb2652919d0 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -138,11 +138,10 @@ static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) static u32 get_reserved(struct intel_gmbus *bus) { struct drm_i915_private *dev_priv = bus->dev_priv; - struct drm_device *dev = &dev_priv->drm; u32 reserved = 0; /* On most chips, these bits must be preserved in software. */ - if (!IS_I830(dev) && !IS_845G(dev)) + if (!IS_I830(dev_priv) && !IS_845G(dev_priv)) reserved = I915_READ_NOTRACE(bus->gpio_reg) & (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); @@ -674,7 +673,7 @@ int intel_setup_gmbus(struct drm_device *dev) bus->reg0 = pin | GMBUS_RATE_100KHZ; /* gmbus seems to be broken on i830 */ - if (IS_I830(dev)) + if (IS_I830(dev_priv)) bus->force_bit = 1; intel_gpio_setup(bus, pin); diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index baaf2ed897ef..1c47f99917e6 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -949,10 +949,8 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; } -static bool intel_lvds_supported(struct drm_device *dev) +static bool intel_lvds_supported(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - /* With the introduction of the PCH we gained a dedicated * LVDS presence pin, use it. */ if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) @@ -960,7 +958,8 @@ static bool intel_lvds_supported(struct drm_device *dev) /* Otherwise LVDS was only attached to mobile products, * except for the inglorious 830gm */ - if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) + if (INTEL_GEN(dev_priv) <= 4 && + IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) return true; return false; @@ -992,7 +991,7 @@ void intel_lvds_init(struct drm_device *dev) int pipe; u8 pin; - if (!intel_lvds_supported(dev)) + if (!intel_lvds_supported(dev_priv)) return; /* Skip init on machines we know falsely report LVDS */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 86051ef2716e..04a38a37af2e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -334,12 +334,12 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; I915_WRITE(DSPFW3, val); POSTING_READ(DSPFW3); - } else if (IS_I945G(dev) || IS_I945GM(dev)) { + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); I915_WRITE(FW_BLC_SELF, val); POSTING_READ(FW_BLC_SELF); - } else if (IS_I915GM(dev)) { + } else if (IS_I915GM(dev_priv)) { /* * FIXME can't find a bit like this for 915G, and * and yet it does have the related watermark in @@ -648,8 +648,10 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) u32 reg; unsigned long wm; - latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, - dev_priv->fsb_freq, dev_priv->mem_freq); + latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), + dev_priv->is_ddr3, + dev_priv->fsb_freq, + dev_priv->mem_freq); if (!latency) { DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); intel_set_memory_cxsr(dev_priv, false); @@ -1579,7 +1581,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); - if (IS_I915GM(dev) && enabled) { + if (IS_I915GM(dev_priv) && enabled) { struct drm_i915_gem_object *obj; obj = intel_fb_obj(enabled->primary->state->fb); @@ -1609,7 +1611,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) unsigned long line_time_us; int entries; - if (IS_I915GM(dev) || IS_I945GM(dev)) + if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) cpp = 4; line_time_us = max(htotal * 1000 / clock, 1); @@ -1623,7 +1625,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) if (srwm < 0) srwm = 1; - if (IS_I945G(dev) || IS_I945GM(dev)) + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); else @@ -6930,7 +6932,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) * The bit 22 of 0x42004 * The bit 7,8,9 of 0x42020. */ - if (IS_IRONLAKE_M(dev)) { + if (IS_IRONLAKE_M(dev_priv)) { /* WaFbcAsynchFlipDisableFbcQueue:ilk */ I915_WRITE(ILK_DISPLAY_CHICKEN1, I915_READ(ILK_DISPLAY_CHICKEN1) | @@ -7340,7 +7342,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) CHICKEN3_DGMG_DONE_FIX_DISABLE); /* WaDisablePSDDualDispatchEnable:ivb */ - if (IS_IVB_GT1(dev)) + if (IS_IVB_GT1(dev_priv)) I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); @@ -7356,7 +7358,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) GEN7_WA_FOR_GEN7_L3_CONTROL); I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); - if (IS_IVB_GT1(dev)) + if (IS_IVB_GT1(dev_priv)) I915_WRITE(GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); else { @@ -7550,7 +7552,7 @@ static void g4x_init_clock_gating(struct drm_device *dev) dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | OVRUNIT_CLOCK_GATE_DISABLE | OVCUNIT_CLOCK_GATE_DISABLE; - if (IS_GM45(dev)) + if (IS_GM45(dev_priv)) dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; I915_WRITE(DSPCLK_GATE_D, dspclk_gate); @@ -7757,7 +7759,7 @@ void intel_init_pm(struct drm_device *dev) vlv_setup_wm_latency(dev); dev_priv->display.update_wm = vlv_update_wm; } else if (IS_PINEVIEW(dev)) { - if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), + if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), dev_priv->is_ddr3, dev_priv->fsb_freq, dev_priv->mem_freq)) { diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 0d9114f9ce27..5fe423571a7e 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1296,7 +1296,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, if (INTEL_INFO(dev)->gen >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ - } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || + IS_G33(dev_priv)) { /* done in crtc_mode_set as it lives inside the dpll register */ } else { sdvox |= (crtc_state->pixel_multiplier - 1) @@ -1389,7 +1390,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, * encoder->get_config we so already have a valid pixel multplier on all * other platfroms. */ - if (IS_I915G(dev) || IS_I915GM(dev)) { + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { pipe_config->pixel_multiplier = ((sdvox & SDVO_PORT_MULTIPLY_MASK) >> SDVO_PORT_MULTIPLY_SHIFT) + 1; @@ -1595,15 +1596,15 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) { - struct drm_device *dev = intel_sdvo->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); uint16_t hotplug; - if (!I915_HAS_HOTPLUG(dev)) + if (!I915_HAS_HOTPLUG(dev_priv)) return 0; /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise * on the line. */ - if (IS_I945G(dev) || IS_I945GM(dev)) + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) return 0; if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 3988c45f9e5f..df16b1dc4c2d 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1095,7 +1095,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT; /* Enable two fixes for the chips that need them. */ - if (IS_I915GM(dev)) + if (IS_I915GM(dev_priv)) tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX; set_tv_mode_timings(dev_priv, tv_mode, burst_ena); @@ -1220,7 +1220,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv, * The TV sense state should be cleared to zero on cantiga platform. Otherwise * the TV is misdetected. This is hardware requirement. */ - if (IS_GM45(dev)) + if (IS_GM45(dev_priv)) tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);