diff mbox

[08/19] drm/i915: Make IS_IVYBRIDGE only take dev_priv

Message ID 1476192112-25336-9-git-send-email-tvrtko.ursulin@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Tvrtko Ursulin Oct. 11, 2016, 1:21 p.m. UTC 
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Saves 848 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 19 +++++++++++--------
 drivers/gpu/drm/i915/i915_drv.h         |  2 +-
 drivers/gpu/drm/i915/i915_gem.c         |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c    | 12 ++++++------
 drivers/gpu/drm/i915/intel_pm.c         | 13 +++++++------
 drivers/gpu/drm/i915/intel_sprite.c     |  2 +-
 7 files changed, 28 insertions(+), 24 deletions(-)

Comments

David Weinehall Oct. 12, 2016, 10:40 a.m. UTC | #1 
On Tue, Oct 11, 2016 at 02:21:41PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Saves 848 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c         | 19 +++++++++++--------
>  drivers/gpu/drm/i915/i915_drv.h         |  2 +-
>  drivers/gpu/drm/i915/i915_gem.c         |  2 +-
>  drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
>  drivers/gpu/drm/i915/intel_display.c    | 12 ++++++------
>  drivers/gpu/drm/i915/intel_pm.c         | 13 +++++++------
>  drivers/gpu/drm/i915/intel_sprite.c     |  2 +-
>  7 files changed, 28 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index bfdbbb745939..f6ba8f262238 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -114,7 +114,7 @@ static bool i915_error_injected(struct drm_i915_private *dev_priv)
>  		      fmt, ##__VA_ARGS__)
>  
>  
> -static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
> +static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
>  {
>  	enum intel_pch ret = PCH_NOP;
>  
> @@ -125,16 +125,16 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
>  	 * make an educated guess as to which PCH is really there.
>  	 */
>  
> -	if (IS_GEN5(dev)) {
> +	if (IS_GEN5(dev_priv)) {
>  		ret = PCH_IBX;
>  		DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
> -	} else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
> +	} else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
>  		ret = PCH_CPT;
>  		DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
> -	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> +	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>  		ret = PCH_LPT;
>  		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
> -	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> +	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>  		ret = PCH_SPT;
>  		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
>  	}
> @@ -178,12 +178,14 @@ static void intel_detect_pch(struct drm_device *dev)
>  			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_CPT;
>  				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> -				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
> +				WARN_ON(!(IS_GEN6(dev_priv) ||
> +					IS_IVYBRIDGE(dev_priv)));
>  			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
>  				/* PantherPoint is CPT compatible */
>  				dev_priv->pch_type = PCH_CPT;
>  				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> -				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
> +				WARN_ON(!(IS_GEN6(dev_priv) ||
> +					IS_IVYBRIDGE(dev_priv)));
>  			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_LPT;
>  				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> @@ -217,7 +219,8 @@ static void intel_detect_pch(struct drm_device *dev)
>  					    PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
>  				    pch->subsystem_device ==
>  					    PCI_SUBDEVICE_ID_QEMU)) {
> -				dev_priv->pch_type = intel_virt_detect_pch(dev);
> +				dev_priv->pch_type =
> +					intel_virt_detect_pch(dev_priv);
>  			} else
>  				continue;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7a40dfa830e7..3f321932d18a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2655,7 +2655,7 @@ struct drm_i915_cmd_table {
>  #define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
>  #define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
>  #define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
> -#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
> +#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.is_ivybridge)
>  #define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
>  				 INTEL_DEVID(dev_priv) == 0x0152 || \
>  				 INTEL_DEVID(dev_priv) == 0x015a)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index afaa49946042..6da841500510 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4364,7 +4364,7 @@ i915_gem_init_hw(struct drm_device *dev)
>  			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>  
>  	if (HAS_PCH_NOP(dev_priv)) {
> -		if (IS_IVYBRIDGE(dev)) {
> +		if (IS_IVYBRIDGE(dev_priv)) {
>  			u32 temp = I915_READ(GEN7_MSG_CTL);
>  			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
>  			I915_WRITE(GEN7_MSG_CTL, temp);
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index df10f4e95736..e117b98c726f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -192,7 +192,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
>  	 * This is only applicable for Ivy Bridge devices since
>  	 * later platforms don't have L3 control bits in the PTE.
>  	 */
> -	if (IS_IVYBRIDGE(dev)) {
> +	if (IS_IVYBRIDGE(to_i915(dev))) {
>  		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
>  		/* Failure shouldn't ever happen this early */
>  		if (WARN_ON(ret)) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ee3b593d3ec2..7894675bfcb8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3729,7 +3729,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>  	/* enable normal train */
>  	reg = FDI_TX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	if (IS_IVYBRIDGE(dev)) {
> +	if (IS_IVYBRIDGE(dev_priv)) {
>  		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
>  		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
>  	} else {
> @@ -3754,7 +3754,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>  	udelay(1000);
>  
>  	/* IVB wants error correction enabled */
> -	if (IS_IVYBRIDGE(dev))
> +	if (IS_IVYBRIDGE(dev_priv))
>  		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
>  			   FDI_FE_ERRC_ENABLE);
>  }
> @@ -4540,7 +4540,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  
>  	assert_pch_transcoder_disabled(dev_priv, pipe);
>  
> -	if (IS_IVYBRIDGE(dev))
> +	if (IS_IVYBRIDGE(dev_priv))
>  		ivybridge_update_fdi_bc_bifurcation(intel_crtc);
>  
>  	/* Write the TU size bits before fdi link training, so that error
> @@ -4854,7 +4854,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
>  		 * as some pre-programmed values are broken,
>  		 * e.g. x201.
>  		 */
> -		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
> +		if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
>  			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
>  						 PF_PIPE_SEL_IVB(pipe));
>  		else
> @@ -12251,7 +12251,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>  		if (fb->modifier[0] != old_fb->modifier[0])
>  			/* vlv: DISPLAY_FLIP fails to change tiling */
>  			engine = NULL;
> -	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
> +	} else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
>  		engine = &dev_priv->engine[BCS];
>  	} else if (INTEL_INFO(dev)->gen >= 7) {
>  		engine = i915_gem_active_get_engine(&obj->last_write,
> @@ -12527,7 +12527,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
>  	 * cstate->update_wm was already set above, so this flag will
>  	 * take effect when we commit and program watermarks.
>  	 */
> -	if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
> +	if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
>  	    needs_scaling(to_intel_plane_state(plane_state)) &&
>  	    !needs_scaling(old_plane_state))
>  		pipe_config->disable_lp_wm = true;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 04a38a37af2e..9155735d01df 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2191,14 +2191,15 @@ static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
>  		wm[0] = 13;
>  }
>  
> -static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
> +static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
> +				       uint16_t wm[5])
>  {
>  	/* ILK cursor LP0 latency is 1300 ns */
> -	if (IS_GEN5(dev))
> +	if (IS_GEN5(dev_priv))
>  		wm[0] = 13;
>  
>  	/* WaDoubleCursorLP3Latency:ivb */
> -	if (IS_IVYBRIDGE(dev))
> +	if (IS_IVYBRIDGE(dev_priv))
>  		wm[3] *= 2;
>  }
>  
> @@ -2294,7 +2295,7 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
>  	       sizeof(dev_priv->wm.pri_latency));
>  
>  	intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
> -	intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
> +	intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
>  
>  	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
>  	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
> @@ -2522,7 +2523,7 @@ static void ilk_wm_merge(struct drm_device *dev,
>  	int last_enabled_level = max_level;
>  
>  	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
> -	if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
> +	if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
>  	    config->num_pipes_active > 1)
>  		last_enabled_level = 0;
>  
> @@ -4617,7 +4618,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
>  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
>  			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
> -	else if (IS_IVYBRIDGE(dev))
> +	else if (IS_IVYBRIDGE(dev_priv))
>  		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
>  			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
>  
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 73a521fdf1bd..d0f798ce6bb2 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1084,7 +1084,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>  
>  	case 7:
>  	case 8:
> -		if (IS_IVYBRIDGE(dev)) {
> +		if (IS_IVYBRIDGE(to_i915(dev))) {
>  			intel_plane->can_scale = true;
>  			intel_plane->max_downscale = 2;
>  		} else {
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bfdbbb745939..f6ba8f262238 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -114,7 +114,7 @@  static bool i915_error_injected(struct drm_i915_private *dev_priv)
 		      fmt, ##__VA_ARGS__)
 
 
-static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
+static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 {
 	enum intel_pch ret = PCH_NOP;
 
@@ -125,16 +125,16 @@  static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 	 * make an educated guess as to which PCH is really there.
 	 */
 
-	if (IS_GEN5(dev)) {
+	if (IS_GEN5(dev_priv)) {
 		ret = PCH_IBX;
 		DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
-	} else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
+	} else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 		ret = PCH_CPT;
 		DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
-	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		ret = PCH_LPT;
 		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
-	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 		ret = PCH_SPT;
 		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 	}
@@ -178,12 +178,14 @@  static void intel_detect_pch(struct drm_device *dev)
 			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CPT;
 				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
-				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
+				WARN_ON(!(IS_GEN6(dev_priv) ||
+					IS_IVYBRIDGE(dev_priv)));
 			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 				/* PantherPoint is CPT compatible */
 				dev_priv->pch_type = PCH_CPT;
 				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
-				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
+				WARN_ON(!(IS_GEN6(dev_priv) ||
+					IS_IVYBRIDGE(dev_priv)));
 			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
 				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
@@ -217,7 +219,8 @@  static void intel_detect_pch(struct drm_device *dev)
 					    PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 				    pch->subsystem_device ==
 					    PCI_SUBDEVICE_ID_QEMU)) {
-				dev_priv->pch_type = intel_virt_detect_pch(dev);
+				dev_priv->pch_type =
+					intel_virt_detect_pch(dev_priv);
 			} else
 				continue;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a40dfa830e7..3f321932d18a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2655,7 +2655,7 @@  struct drm_i915_cmd_table {
 #define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
 #define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
 #define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
-#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
+#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.is_ivybridge)
 #define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
 				 INTEL_DEVID(dev_priv) == 0x0152 || \
 				 INTEL_DEVID(dev_priv) == 0x015a)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index afaa49946042..6da841500510 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4364,7 +4364,7 @@  i915_gem_init_hw(struct drm_device *dev)
 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
 	if (HAS_PCH_NOP(dev_priv)) {
-		if (IS_IVYBRIDGE(dev)) {
+		if (IS_IVYBRIDGE(dev_priv)) {
 			u32 temp = I915_READ(GEN7_MSG_CTL);
 			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
 			I915_WRITE(GEN7_MSG_CTL, temp);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index df10f4e95736..e117b98c726f 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -192,7 +192,7 @@  i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
 	 * This is only applicable for Ivy Bridge devices since
 	 * later platforms don't have L3 control bits in the PTE.
 	 */
-	if (IS_IVYBRIDGE(dev)) {
+	if (IS_IVYBRIDGE(to_i915(dev))) {
 		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
 		/* Failure shouldn't ever happen this early */
 		if (WARN_ON(ret)) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ee3b593d3ec2..7894675bfcb8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3729,7 +3729,7 @@  static void intel_fdi_normal_train(struct drm_crtc *crtc)
 	/* enable normal train */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
-	if (IS_IVYBRIDGE(dev)) {
+	if (IS_IVYBRIDGE(dev_priv)) {
 		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
 		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
 	} else {
@@ -3754,7 +3754,7 @@  static void intel_fdi_normal_train(struct drm_crtc *crtc)
 	udelay(1000);
 
 	/* IVB wants error correction enabled */
-	if (IS_IVYBRIDGE(dev))
+	if (IS_IVYBRIDGE(dev_priv))
 		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
 			   FDI_FE_ERRC_ENABLE);
 }
@@ -4540,7 +4540,7 @@  static void ironlake_pch_enable(struct drm_crtc *crtc)
 
 	assert_pch_transcoder_disabled(dev_priv, pipe);
 
-	if (IS_IVYBRIDGE(dev))
+	if (IS_IVYBRIDGE(dev_priv))
 		ivybridge_update_fdi_bc_bifurcation(intel_crtc);
 
 	/* Write the TU size bits before fdi link training, so that error
@@ -4854,7 +4854,7 @@  static void ironlake_pfit_enable(struct intel_crtc *crtc)
 		 * as some pre-programmed values are broken,
 		 * e.g. x201.
 		 */
-		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+		if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
 			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
 						 PF_PIPE_SEL_IVB(pipe));
 		else
@@ -12251,7 +12251,7 @@  static int intel_crtc_page_flip(struct drm_crtc *crtc,
 		if (fb->modifier[0] != old_fb->modifier[0])
 			/* vlv: DISPLAY_FLIP fails to change tiling */
 			engine = NULL;
-	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
+	} else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
 		engine = &dev_priv->engine[BCS];
 	} else if (INTEL_INFO(dev)->gen >= 7) {
 		engine = i915_gem_active_get_engine(&obj->last_write,
@@ -12527,7 +12527,7 @@  int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
 	 * cstate->update_wm was already set above, so this flag will
 	 * take effect when we commit and program watermarks.
 	 */
-	if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
+	if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
 	    needs_scaling(to_intel_plane_state(plane_state)) &&
 	    !needs_scaling(old_plane_state))
 		pipe_config->disable_lp_wm = true;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 04a38a37af2e..9155735d01df 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2191,14 +2191,15 @@  static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
 		wm[0] = 13;
 }
 
-static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
+static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
+				       uint16_t wm[5])
 {
 	/* ILK cursor LP0 latency is 1300 ns */
-	if (IS_GEN5(dev))
+	if (IS_GEN5(dev_priv))
 		wm[0] = 13;
 
 	/* WaDoubleCursorLP3Latency:ivb */
-	if (IS_IVYBRIDGE(dev))
+	if (IS_IVYBRIDGE(dev_priv))
 		wm[3] *= 2;
 }
 
@@ -2294,7 +2295,7 @@  static void ilk_setup_wm_latency(struct drm_device *dev)
 	       sizeof(dev_priv->wm.pri_latency));
 
 	intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
-	intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
+	intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
 
 	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
 	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
@@ -2522,7 +2523,7 @@  static void ilk_wm_merge(struct drm_device *dev,
 	int last_enabled_level = max_level;
 
 	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
-	if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
+	if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
 	    config->num_pipes_active > 1)
 		last_enabled_level = 0;
 
@@ -4617,7 +4618,7 @@  void ilk_wm_get_hw_state(struct drm_device *dev)
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
 			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
-	else if (IS_IVYBRIDGE(dev))
+	else if (IS_IVYBRIDGE(dev_priv))
 		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
 			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 73a521fdf1bd..d0f798ce6bb2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1084,7 +1084,7 @@  intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 
 	case 7:
 	case 8:
-		if (IS_IVYBRIDGE(dev)) {
+		if (IS_IVYBRIDGE(to_i915(dev))) {
 			intel_plane->can_scale = true;
 			intel_plane->max_downscale = 2;
 		} else {