From patchwork Wed Oct 19 00:05:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 9383365 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B74F1600CA for ; Wed, 19 Oct 2016 00:05:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6AA3288D6 for ; Wed, 19 Oct 2016 00:05:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9716C28BDB; Wed, 19 Oct 2016 00:05:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0E9E0288D6 for ; Wed, 19 Oct 2016 00:05:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E6B86E7DB; Wed, 19 Oct 2016 00:05:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93EC36E7DB for ; Wed, 19 Oct 2016 00:05:51 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP; 18 Oct 2016 17:05:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,364,1473145200"; d="scan'208";a="21113874" Received: from nuc-skylake.jf.intel.com ([10.54.75.23]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2016 17:05:38 -0700 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Oct 2016 17:05:19 -0700 Message-Id: <1476835519-7310-1-git-send-email-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <20161018090805.GY4329@intel.com> References: <20161018090805.GY4329@intel.com> Cc: Dhinakaran Pandiyan Subject: [Intel-gfx] [i-g-t PATCH v2] igt/tools: Update intel_watermark with SKL support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Added support to print SKL watermark and DDB registers. v2: Printed raw register data, renamed planes and combined two printf()'s (Ville) Signed-off-by: Dhinakaran Pandiyan --- tools/intel_watermark.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 1 deletion(-) diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c index e9a2b05..81e394c 100644 --- a/tools/intel_watermark.c +++ b/tools/intel_watermark.c @@ -120,6 +120,11 @@ static const char *endis(bool enabled) return enabled ? "enabled" : "disabled"; } +static const char endis_ast(bool enabled) +{ + return enabled ? '*' : ' '; +} + static int is_gen7_plus(uint32_t d) { return !(IS_GEN5(d) || IS_GEN6(d)); @@ -130,6 +135,147 @@ static int is_hsw_plus(uint32_t d) return !(IS_GEN5(d) || IS_GEN6(d) || IS_IVYBRIDGE(d)); } + +static void skl_wm_dump(void) +{ + int pipe, plane, level; + int num_pipes = 3; + int num_planes = 5; + int num_levels = 8; + uint32_t base_addr = 0x70000, addr, wm_offset; + uint32_t wm[num_levels][num_pipes][num_planes]; + uint32_t wm_trans[num_pipes][num_planes]; + uint32_t buf_cfg[num_pipes][num_planes]; + char reg_name[20]; + + intel_register_access_init(intel_get_pci_device(), 0); + + for (pipe = 0; pipe < num_pipes; pipe++) { + for (plane = 0; plane < num_planes; plane++) { + addr = base_addr + pipe * 0x1000 + plane * 0x100; + + wm_trans[pipe][plane] = read_reg(addr + 0x00168); + buf_cfg[pipe][plane] = read_reg(addr + 0x0017C); + for (level = 0; level < num_levels; level++) { + wm_offset = addr + 0x00140 + level * 0x4; + wm[level][pipe][plane] = read_reg(wm_offset); + } + } + } + + for (plane = 0; plane < num_planes; plane++) { + for (level = 0; level < num_levels; level++) { + for (pipe = 0; pipe < num_pipes; pipe++) { + if (plane == 0) + snprintf(reg_name, sizeof(reg_name), "%s_WM_%c_%1d","CUR", + pipe_name(pipe), level); + else + snprintf(reg_name, sizeof(reg_name), "%s_WM_%1d_%c_%1d","PLANE", + plane, pipe_name(pipe), level); + + printf("%-19s %8x\t\t" , reg_name, wm[level][pipe][plane]); + } + printf("\n"); + } + printf("\n"); + } + + for (plane = 0; plane < num_planes; plane++) { + for (pipe = 0; pipe < num_pipes; pipe++) { + if (plane == 0) + snprintf(reg_name, sizeof(reg_name), "%s_WM_TRANS_%c", "CUR", + pipe_name(pipe)); + else + snprintf(reg_name, sizeof(reg_name), "%s_WM_TRANS_%1d_%c", "PLANE", + plane, pipe_name(pipe)); + + printf("%-19s %8x\t\t", reg_name, wm_trans[pipe][plane]); + + } + printf("\n"); + } + printf("\n"); + + for (plane = 0; plane < num_planes; plane++) { + for (pipe = 0; pipe < num_pipes; pipe++) { + if (plane == 0) + snprintf(reg_name, sizeof(reg_name), "%s_BUF_CFG_%c", "CUR", + pipe_name(pipe)); + else + snprintf(reg_name, sizeof(reg_name), "%s_BUF_CFG_%1d_%c", "PLANE", + plane, pipe_name(pipe)); + + printf("%-19s %8x\t\t", reg_name, buf_cfg[pipe][plane]); + } + printf("\n"); + } + printf("\n"); + + for (pipe = 0; pipe < num_pipes; pipe++) { + uint32_t start, end, size; + uint32_t lines, blocks, enable; + + printf("PIPE_%c\n", pipe_name(pipe)); + printf("LEVEL CURSOR PLANE_1 PLANE_2 PLANE_3 PLANE_4\n"); + for (level = 0; level < num_levels; level++) { + printf("%5d ", level); + for (plane = 0; plane < num_planes; plane++) { + blocks = REG_DECODE1(wm[level][pipe][plane], 0, 9); + lines = REG_DECODE1(wm[level][pipe][plane], 14, 5); + enable = REG_DECODE1(wm[level][pipe][plane], 31, 1); + + printf("%3d%c", blocks, endis_ast(enable)); + if (!REG_DECODE1(wm[level][pipe][plane], 30, 1)) + printf("(%2d) ", lines); + else + printf("(--) "); + } + printf("\n"); + } + + printf("TRANS: "); + for (plane = 0; plane < num_planes; plane++) { + blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 9); + lines = REG_DECODE1(wm_trans[pipe][plane], 14, 5); + enable = REG_DECODE1(wm_trans[pipe][plane], 31, 1); + + printf("%3d%c", blocks, endis_ast(enable)); + if (!REG_DECODE1(wm_trans[pipe][plane], 30, 1)) + printf("(%2d) ", lines); + else + printf("(--) "); + } + + printf("\nDDB allocation:"); + + printf("\nstart "); + for (plane = 0; plane < num_planes; plane++) { + start = REG_DECODE1(buf_cfg[pipe][plane], 0, 10); + printf("%7d ", start); + } + + printf("\nend "); + for (plane = 0; plane < num_planes; plane++) { + end = REG_DECODE1(buf_cfg[pipe][plane], 16, 10); + printf("%7d ", end); + } + + printf("\nsize "); + for (plane = 0; plane < num_planes; plane++) { + start = REG_DECODE1(buf_cfg[pipe][plane], 0, 10); + end = REG_DECODE1(buf_cfg[pipe][plane], 16, 10); + size = end - start + 1; + printf("%7d ", (end == 0 && size == 1) ? 0 : size); + } + + printf("\n\n\n"); + } + + printf("* plane watermark enabled\n"); + printf("(x) line watermark if enabled\n"); + +} + static void ilk_wm_dump(void) { int i; @@ -900,7 +1046,9 @@ int main(int argc, char *argv[]) { devid = intel_get_pci_device()->device_id; - if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) { + if (IS_GEN9(devid)) { + skl_wm_dump(); + } else if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) { display_base = 0x180000; vlv_wm_dump(); } else if (HAS_PCH_SPLIT(devid)) {