From patchwork Wed Oct 19 21:46:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 9385471 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1B025600CA for ; Wed, 19 Oct 2016 21:45:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A30C28DBC for ; Wed, 19 Oct 2016 21:45:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F2E8E28DE4; Wed, 19 Oct 2016 21:45:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8417B28DBC for ; Wed, 19 Oct 2016 21:45:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0C0146EA07; Wed, 19 Oct 2016 21:45:42 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8EEC96E9F1; Wed, 19 Oct 2016 21:45:25 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 19 Oct 2016 14:45:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,516,1473145200"; d="scan'208";a="21832210" Received: from manasi-otcmedia.jf.intel.com ([10.7.199.175]) by orsmga004.jf.intel.com with ESMTP; 19 Oct 2016 14:45:23 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Wed, 19 Oct 2016 14:46:23 -0700 Message-Id: <1476913584-16948-8-git-send-email-manasi.d.navare@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476913584-16948-1-git-send-email-manasi.d.navare@intel.com> References: <1476913584-16948-1-git-send-email-manasi.d.navare@intel.com> Cc: dri-devel@lists.freedesktop.org, daniel.vetter@intel.com Subject: [Intel-gfx] [PATCH RFC 7/8] drm/i915: Link Rate fallback on Link training failure X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If link training at a link rate optimal for a particular mode fails during modeset's atomic commit phase, then we let the modeset complete and then retry. We save the link rate value at which link training failed and use a lower link rate to prune the modes during the next modeset, configure the pipe at lower link rate and retrian at lower link rate. This is also required to pass DP CTS tests 4.3.1.3, 4.3.1.4, 4.3.1.6. Cc: Jani Nikula Cc: Daniel Vetter Cc: Ville Syrjala Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/intel_ddi.c | 14 ++++++++++- drivers/gpu/drm/i915/intel_dp.c | 35 +++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_dp_link_training.c | 12 ++++++--- drivers/gpu/drm/i915/intel_drv.h | 6 ++++- 4 files changed, 60 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 7f7741c..cccb301 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1642,6 +1642,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = intel_ddi_get_encoder_port(encoder); + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; intel_dp_set_link_params(intel_dp, link_rate, lane_count, link_mst); @@ -1652,7 +1654,17 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, intel_prepare_dp_ddi_buffers(encoder); intel_ddi_init_dp_buf_reg(encoder); intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); - intel_dp_start_link_train(intel_dp); + if (!intel_dp_start_link_train(intel_dp)) { + DRM_ERROR("Link Training failed at link rate = %d, lane count = %d", + link_rate, lane_count); + intel_dp->link_train_failed = true; + intel_dp->link_train_failed_link_rate = link_rate; + intel_dp->link_train_failed_lane_count = lane_count; + /* Schedule a Hotplug Uevent to userspace to start modeset */ + schedule_work(&connector->i915_modeset_retry_work); + } else + connector->link_train_retry = false; + if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index aae7f82..78246ba 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -313,6 +313,7 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int *common_rates int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk; + int common_rates[DP_MAX_SUPPORTED_RATES] = {}; max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); @@ -326,8 +327,26 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int *common_rates target_clock = fixed_mode->clock; } - max_link_clock = intel_dp_max_link_rate(intel_dp); - max_lanes = intel_dp_max_lane_count(intel_dp); + /* Prune the modes based on the link rate that failed */ + if (intel_dp->link_train_failed_link_rate) { + intel_dp->link_rate_index = intel_dp_link_rate_index(intel_dp, + common_rates, + intel_dp->link_train_failed_link_rate); + if (intel_dp->link_rate_index > 0) { + max_link_clock = common_rates[intel_dp->link_rate_index - 1]; + max_lanes = intel_dp_max_lane_count(intel_dp); + } else { + /* Here we can lower the lane count, but that is DP 1.3 not 1.2 */ + DRM_ERROR(" No Valid Mode Supported for this Link"); + connector->link_train_retry = false; + intel_dp->link_train_failed_link_rate = 0; + intel_dp->link_rate_index = -1; + } + } + else { + max_link_clock = intel_dp_max_link_rate(intel_dp); + max_lanes = intel_dp_max_lane_count(intel_dp); + } max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); mode_rate = intel_dp_link_required(target_clock, 18); @@ -1610,6 +1629,14 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) return false; + /* Fall back to lower link rate in case of failure in previous modeset */ + if (intel_dp->link_train_failed_link_rate) { + min_lane_count = max_lane_count; + min_clock = max_clock = intel_dp->link_rate_index - 1; + intel_dp->link_train_failed_link_rate = 0; + intel_dp->link_rate_index = -1; + } + DRM_DEBUG_KMS("DP link computation with max lane count %i " "max bw %d pixel clock %iKHz\n", max_lane_count, common_rates[max_clock], @@ -4394,6 +4421,10 @@ static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, /* Can't disconnect eDP, but you can close the lid... */ if (is_edp(intel_dp)) status = edp_detect(intel_dp); + else if (intel_dp->link_train_failed) { + intel_dp->link_train_failed = false; + goto out; + } else if (intel_digital_port_connected(to_i915(dev), dp_to_dig_port(intel_dp))) status = intel_dp_detect_dpcd(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index 0048b52..10f81ab 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -310,9 +310,15 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp) DP_TRAINING_PATTERN_DISABLE); } -void +bool intel_dp_start_link_train(struct intel_dp *intel_dp) { - intel_dp_link_training_clock_recovery(intel_dp); - intel_dp_link_training_channel_equalization(intel_dp); + bool ret; + + if (intel_dp_link_training_clock_recovery(intel_dp)) { + ret = intel_dp_link_training_channel_equalization(intel_dp); + if (ret) + return true; + } + return false; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5760420..4b4bed6 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -890,6 +890,10 @@ struct intel_dp { uint32_t DP; int link_rate; uint8_t lane_count; + int link_train_failed_link_rate; + uint8_t link_train_failed_lane_count; + int link_rate_index; + bool link_train_failed; uint8_t sink_count; bool link_mst; bool has_audio; @@ -1403,7 +1407,7 @@ bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, uint8_t lane_count, bool link_mst); -void intel_dp_start_link_train(struct intel_dp *intel_dp); +bool intel_dp_start_link_train(struct intel_dp *intel_dp); void intel_dp_stop_link_train(struct intel_dp *intel_dp); void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); void intel_dp_encoder_reset(struct drm_encoder *encoder);