| Message ID | 1477065346-13736-2-git-send-email-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Oct 21, 2016 at 01:55:46PM -0200, Paulo Zanoni wrote: > Its size is 11:0 instead of 10:0. Found by inspecting the spec. I'm > not aware of any real-world IGT failures caused by this. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 10 ++++++---- > drivers/gpu/drm/i915/i915_reg.h | 5 +++-- > 2 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index dc057c7..b54ff40 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1674,11 +1674,13 @@ static int i915_fbc_status(struct seq_file *m, void *unused) > seq_printf(m, "FBC disabled: %s\n", > dev_priv->fbc.no_fbc_reason); > > - if (intel_fbc_is_active(dev_priv) && > - INTEL_GEN(dev_priv) >= 7) > + if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { > + uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? > + BDW_FBC_COMPRESSION_MASK : > + IVB_FBC_COMPRESSION_MASK; > seq_printf(m, "Compressing: %s\n", > - yesno(I915_READ(FBC_STATUS2) & > - FBC_COMPRESSION_MASK)); > + yesno(I915_READ(FBC_STATUS2) & mask)); > + } > > mutex_unlock(&dev_priv->fbc.lock); > intel_runtime_pm_put(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 00efaa1..a9be3f0 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2188,8 +2188,9 @@ enum skl_disp_power_wells { > #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ > #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) > > -#define FBC_STATUS2 _MMIO(0x43214) > -#define FBC_COMPRESSION_MASK 0x7ff > +#define FBC_STATUS2 _MMIO(0x43214) > +#define IVB_FBC_COMPRESSION_MASK 0x7ff > +#define BDW_FBC_COMPRESSION_MASK 0xfff I'm not sure this mask is doing us any good since the high bits are all MBZ anyway. But this matches the spec so Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > #define FBC_LL_SIZE (1536) > > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index dc057c7..b54ff40 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1674,11 +1674,13 @@ static int i915_fbc_status(struct seq_file *m, void *unused) seq_printf(m, "FBC disabled: %s\n", dev_priv->fbc.no_fbc_reason); - if (intel_fbc_is_active(dev_priv) && - INTEL_GEN(dev_priv) >= 7) + if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { + uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? + BDW_FBC_COMPRESSION_MASK : + IVB_FBC_COMPRESSION_MASK; seq_printf(m, "Compressing: %s\n", - yesno(I915_READ(FBC_STATUS2) & - FBC_COMPRESSION_MASK)); + yesno(I915_READ(FBC_STATUS2) & mask)); + } mutex_unlock(&dev_priv->fbc.lock); intel_runtime_pm_put(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 00efaa1..a9be3f0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2188,8 +2188,9 @@ enum skl_disp_power_wells { #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) -#define FBC_STATUS2 _MMIO(0x43214) -#define FBC_COMPRESSION_MASK 0x7ff +#define FBC_STATUS2 _MMIO(0x43214) +#define IVB_FBC_COMPRESSION_MASK 0x7ff +#define BDW_FBC_COMPRESSION_MASK 0xfff #define FBC_LL_SIZE (1536)
Its size is 11:0 instead of 10:0. Found by inspecting the spec. I'm not aware of any real-world IGT failures caused by this. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 10 ++++++---- drivers/gpu/drm/i915/i915_reg.h | 5 +++-- 2 files changed, 9 insertions(+), 6 deletions(-)