From patchwork Tue Oct 25 04:18:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 9393949 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C32226077A for ; Tue, 25 Oct 2016 04:19:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B414729177 for ; Tue, 25 Oct 2016 04:19:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A6D4D292C7; Tue, 25 Oct 2016 04:19:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 64BD229177 for ; Tue, 25 Oct 2016 04:19:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE30A6E646; Tue, 25 Oct 2016 04:19:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id DCABD6E643 for ; Tue, 25 Oct 2016 04:19:02 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP; 24 Oct 2016 21:19:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,544,1473145200"; d="scan'208";a="23627521" Received: from nuc-skylake.jf.intel.com ([10.54.75.23]) by orsmga004.jf.intel.com with ESMTP; 24 Oct 2016 21:19:02 -0700 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Oct 2016 21:18:37 -0700 Message-Id: <1477369117-24627-3-git-send-email-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477369117-24627-1-git-send-email-dhinakaran.pandiyan@intel.com> References: <1477369117-24627-1-git-send-email-dhinakaran.pandiyan@intel.com> Cc: Paulo Zanoni , Jani Nikula , Jeeja KP , Libin Yang , Dhinakaran Pandiyan Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: BDW cdclk fix for DP audio X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP According to BSpec, cdclk has to be not less than 432 MHz with DP audio enabled, port width x4, and link rate HBR2 (5.4 GHz) Having a lower cdclk triggers pipe underruns, which then lead to displays continuously cycling off and on. This is essential for DP MST audio as the link is trained at HBR2 and 4 lanes by default. v2: Restrict fix to BDW Retain the set cdclk across modesets (Ville) Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a94f7d1..8c59651 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10260,6 +10260,18 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) bxt_set_cdclk(to_i915(dev), req_cdclk); } +static unsigned int bdw_dp_audio_cdclk(struct intel_crtc_state *crtc_state) +{ + + if (intel_crtc_has_dp_encoder(crtc_state) && + crtc_state->has_audio && + crtc_state->port_clock >= 540000 && + crtc_state->lane_count == 4) + return 432000; + + return 0; +} + /* compute the max rate for new configuration */ static int ilk_max_pixel_rate(struct drm_atomic_state *state) { @@ -10275,7 +10287,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) sizeof(intel_state->min_pixclk)); for_each_crtc_in_state(state, crtc, cstate, i) { - int pixel_rate; + unsigned int pixel_rate; crtc_state = to_intel_crtc_state(cstate); if (!crtc_state->base.enable) { @@ -10285,9 +10297,19 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) pixel_rate = ilk_pipe_pixel_rate(crtc_state); + if (IS_BROADWELL(dev_priv)) { /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); + if (crtc_state->ips_enabled) + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); + + /* BSpec says "Do not use DisplayPort with CDCLK less than + * 432 MHz, audio enabled, port width x4, and link rate + * HBR2 (5.4 GHz), or else there may be audio corruption or + * screen corruption." + */ + pixel_rate = max(pixel_rate, + bdw_dp_audio_cdclk(crtc_state)); + } intel_state->min_pixclk[i] = pixel_rate; }