From patchwork Wed Oct 26 02:37:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 9399065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9B76760588 for ; Thu, 27 Oct 2016 08:57:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 82E6429BD3 for ; Thu, 27 Oct 2016 08:57:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7813029BEB; Thu, 27 Oct 2016 08:57:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EF60C29BD3 for ; Thu, 27 Oct 2016 08:57:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 20E766EB77; Thu, 27 Oct 2016 08:53:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B8C56E7A4 for ; Wed, 26 Oct 2016 02:38:02 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 25 Oct 2016 19:38:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.31,548,1473145200"; d="scan'208"; a="1075788875" Received: from nuc-skylake.jf.intel.com ([10.54.75.23]) by fmsmga002.fm.intel.com with ESMTP; 25 Oct 2016 19:38:01 -0700 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Tue, 25 Oct 2016 19:37:36 -0700 Message-Id: <1477449456-22146-1-git-send-email-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477442271.19344.41.camel@dk-H97M-D3H> References: <1477442271.19344.41.camel@dk-H97M-D3H> Cc: Jani Nikula , Dhinakaran Pandiyan Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Enable DP audio stall fix for gen9 platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Enabling DP audio stall fix is necessary to play audio over DP HBR2. So, let's set this bit right before enabling the audio codec. Playing audio without setting this bit results in pipe FIFO underruns. This workaround is applicable only for audio sample rates up to 96kHz. For frequencies above 96kHz, this is insufficient and cdclk should be increased to at least 432 MHz, just like BDW. Since, the audio driver does not support sample rates > 48 kHz, we are safe with this fix for now. v2: Inlined the code change within hsw_audio_codec_enable() (Jani) Fixed the port clock typo Added TODO comment Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_audio.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 00efaa1..76dac48 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6236,6 +6236,11 @@ enum { #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) +#define _CHICKEN_TRANS_A 0x420C0 +#define _CHICKEN_TRANS_B 0x420C4 +#define CHICKEN_TRANS(tran) _MMIO_TRANS(tran, _CHICKEN_TRANS_A, _CHICKEN_TRANS_B) +#define SPARE_13 (1<<13) + /* WaCatErrorRejectionIssue */ #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 7093cfb..894f11e 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -283,6 +283,8 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + struct intel_crtc_state *crtc_config = intel_crtc->config; + enum transcoder cpu_transcoder = crtc_config->cpu_transcoder; enum pipe pipe = intel_crtc->pipe; uint32_t tmp; @@ -290,13 +292,21 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder) mutex_lock(&dev_priv->av_mutex); + /*Disable DP audio stall fix for HBR2*/ + if (IS_GEN9(dev_priv) && intel_crtc_has_dp_encoder(crtc_config) && + crtc_config->port_clock >= 540000) { + tmp = I915_READ(CHICKEN_TRANS(cpu_transcoder)); + tmp &= ~SPARE_13; + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), tmp); + } + /* Disable timestamps */ tmp = I915_READ(HSW_AUD_CFG(pipe)); tmp &= ~AUD_CONFIG_N_VALUE_INDEX; tmp |= AUD_CONFIG_N_PROG_ENABLE; tmp &= ~AUD_CONFIG_UPPER_N_MASK; tmp &= ~AUD_CONFIG_LOWER_N_MASK; - if (intel_crtc_has_dp_encoder(intel_crtc->config)) + if (intel_crtc_has_dp_encoder(crtc_config)) tmp |= AUD_CONFIG_N_VALUE_INDEX; I915_WRITE(HSW_AUD_CFG(pipe), tmp); @@ -315,6 +325,8 @@ static void hsw_audio_codec_enable(struct drm_connector *connector, { struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); + struct intel_crtc_state *crtc_config = intel_crtc->config; + enum transcoder cpu_transcoder = crtc_config->cpu_transcoder; enum pipe pipe = intel_crtc->pipe; enum port port = intel_encoder->port; const uint8_t *eld = connector->eld; @@ -326,6 +338,22 @@ static void hsw_audio_codec_enable(struct drm_connector *connector, mutex_lock(&dev_priv->av_mutex); + /* Enable DP audio stall fix for HBR2 + * + * TODO: This workaround is applicable only for audio sample rates up + * to 96kHz. For frequencies above 96kHz, this is insufficient and + * cdclk should be increased to at least 432 MHz, just like BDW. Since, + * the audio driver does not support sample rates > 48 kHz, we are safe + * with this fix for now. + */ + + if (IS_GEN9(dev_priv) && intel_crtc_has_dp_encoder(crtc_config) && + crtc_config->port_clock >= 540000) { + tmp = I915_READ(CHICKEN_TRANS(cpu_transcoder)); + tmp |= SPARE_13; + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), tmp); + } + /* Enable audio presence detect, invalidate ELD */ tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); tmp |= AUDIO_OUTPUT_ENABLE(pipe);