diff mbox

[v4,2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms

Message ID 1478026080-2925-2-git-send-email-dhinakaran.pandiyan@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Dhinakaran Pandiyan Nov. 1, 2016, 6:48 p.m. UTC 
According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.

Let's apply this work around to GEN9 platforms too, as it fixes the same
issue.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
Cc: stable@vger.kernel.org
Cc: Libin Yang <libin.yang@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Jani Nikula Nov. 1, 2016, 7:35 p.m. UTC | #1 
On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> cycling on/off.
>
> Let's apply this work around to GEN9 platforms too, as it fixes the same
> issue.

I'm too tired to read bspec now, but is gen9 really the answer, or just
Skylake?


>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
> Cc: stable@vger.kernel.org
> Cc: Libin Yang <libin.yang@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 37483ee..c0ae147 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>  static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>  					  int pixel_rate)
>  {
> +	struct drm_device *dev = crtc_state->base.crtc->dev;

Nitpick, I guess I'd make that

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

but no big deal.

> +
>  	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> -	if (crtc_state->ips_enabled)
> +	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
>  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
>  
>  	/* BSpec says "Do not use DisplayPort with CDCLK less than
> @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>  
>  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>  
> -		if (IS_BROADWELL(dev_priv))
> +		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
>  			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
>  								    pixel_rate);
Dhinakaran Pandiyan Nov. 1, 2016, 7:42 p.m. UTC | #2 
On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:
> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:

> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP

> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less

> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays

> > cycling on/off.

> >

> > Let's apply this work around to GEN9 platforms too, as it fixes the same

> > issue.

> 

> I'm too tired to read bspec now, but is gen9 really the answer, or just

> Skylake?

> 

> 


Gen9, applies to BXT and KBL as well. 

-DK

> >

> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907

> > Cc: stable@vger.kernel.org

> > Cc: Libin Yang <libin.yang@linux.intel.com>

> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> > ---

> >  drivers/gpu/drm/i915/intel_display.c | 6 ++++--

> >  1 file changed, 4 insertions(+), 2 deletions(-)

> >

> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

> > index 37483ee..c0ae147 100644

> > --- a/drivers/gpu/drm/i915/intel_display.c

> > +++ b/drivers/gpu/drm/i915/intel_display.c

> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)

> >  static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,

> >  					  int pixel_rate)

> >  {

> > +	struct drm_device *dev = crtc_state->base.crtc->dev;

> 

> Nitpick, I guess I'd make that

> 

> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

> 

> but no big deal.

> 

> > +

> >  	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

> > -	if (crtc_state->ips_enabled)

> > +	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)

> >  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);

> >  

> >  	/* BSpec says "Do not use DisplayPort with CDCLK less than

> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)

> >  

> >  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);

> >  

> > -		if (IS_BROADWELL(dev_priv))

> > +		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))

> >  			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,

> >  								    pixel_rate);

>
Jani Nikula Nov. 1, 2016, 7:50 p.m. UTC | #3 
On Tue, 01 Nov 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:
>> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
>> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
>> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
>> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
>> > cycling on/off.
>> >
>> > Let's apply this work around to GEN9 platforms too, as it fixes the same
>> > issue.
>> 
>> I'm too tired to read bspec now, but is gen9 really the answer, or just
>> Skylake?
>> 
>> 
>
> Gen9, applies to BXT and KBL as well.

I'll take your word for it, and with that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



>
> -DK
>
>> >
>> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
>> > Cc: stable@vger.kernel.org
>> > Cc: Libin Yang <libin.yang@linux.intel.com>
>> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_display.c | 6 ++++--
>> >  1 file changed, 4 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> > index 37483ee..c0ae147 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> >  static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>> >  					  int pixel_rate)
>> >  {
>> > +	struct drm_device *dev = crtc_state->base.crtc->dev;
>> 
>> Nitpick, I guess I'd make that
>> 
>> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>> 
>> but no big deal.
>> 
>> > +
>> >  	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
>> > -	if (crtc_state->ips_enabled)
>> > +	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
>> >  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
>> >  
>> >  	/* BSpec says "Do not use DisplayPort with CDCLK less than
>> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>> >  
>> >  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>> >  
>> > -		if (IS_BROADWELL(dev_priv))
>> > +		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
>> >  			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
>> >  								    pixel_rate);
>> 
>
Dhinakaran Pandiyan Nov. 2, 2016, 8:15 p.m. UTC | #4 
On Tue, 2016-11-01 at 21:50 +0200, Jani Nikula wrote:
> On Tue, 01 Nov 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:

> > On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:

> >> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:

> >> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP

> >> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less

> >> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays

> >> > cycling on/off.

> >> >

> >> > Let's apply this work around to GEN9 platforms too, as it fixes the same

> >> > issue.

> >> 

> >> I'm too tired to read bspec now, but is gen9 really the answer, or just

> >> Skylake?

> >> 

> >> 

> >

> > Gen9, applies to BXT and KBL as well.

> 

> I'll take your word for it, and with that,

> 

> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> 

> 

> 


Thanks for the review. 
> >

> > -DK

> >

> >> >

> >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907

> >> > Cc: stable@vger.kernel.org

> >> > Cc: Libin Yang <libin.yang@linux.intel.com>

> >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> >> > ---

> >> >  drivers/gpu/drm/i915/intel_display.c | 6 ++++--

> >> >  1 file changed, 4 insertions(+), 2 deletions(-)

> >> >

> >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

> >> > index 37483ee..c0ae147 100644

> >> > --- a/drivers/gpu/drm/i915/intel_display.c

> >> > +++ b/drivers/gpu/drm/i915/intel_display.c

> >> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)

> >> >  static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,

> >> >  					  int pixel_rate)

> >> >  {

> >> > +	struct drm_device *dev = crtc_state->base.crtc->dev;

> >> 

> >> Nitpick, I guess I'd make that

> >> 

> >> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

> >> 

> >> but no big deal.

> >> 

> >> > +

> >> >  	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

> >> > -	if (crtc_state->ips_enabled)

> >> > +	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)

> >> >  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);

> >> >  

> >> >  	/* BSpec says "Do not use DisplayPort with CDCLK less than

> >> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)

> >> >  

> >> >  		pixel_rate = ilk_pipe_pixel_rate(crtc_state);

> >> >  

> >> > -		if (IS_BROADWELL(dev_priv))

> >> > +		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))

> >> >  			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,

> >> >  								    pixel_rate);

> >> 

> >

>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 37483ee..c0ae147 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10264,8 +10264,10 @@  static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
 					  int pixel_rate)
 {
+	struct drm_device *dev = crtc_state->base.crtc->dev;
+
 	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-	if (crtc_state->ips_enabled)
+	if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
 		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
 
 	/* BSpec says "Do not use DisplayPort with CDCLK less than
@@ -10307,7 +10309,7 @@  static int ilk_max_pixel_rate(struct drm_atomic_state *state)
 
 		pixel_rate = ilk_pipe_pixel_rate(crtc_state);
 
-		if (IS_BROADWELL(dev_priv))
+		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
 			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
 								    pixel_rate);