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[v3] drm/i915/glk: Introduce Geminilake platform definition

Message ID 1479133526-32389-1-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ander Conselvan de Oliveira Nov. 14, 2016, 2:25 p.m. UTC 
Geminilake is an Intel® Processor containing Intel® HD Graphics
following Broxton.

Let's start by adding the platform definition. PCI IDs and plaform
specific code will follow.

v2: Rebase (don't allow dev to be used with the new macro).

v3: Update ddb size. (Matt)
    Rebase on s/preliminary_hw/alpha/

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 drivers/gpu/drm/i915/i915_pci.c | 7 +++++++
 2 files changed, 9 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4a14de..29a2d2a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -654,6 +654,7 @@  struct intel_csr {
 	func(is_broadwell); \
 	func(is_skylake); \
 	func(is_broxton); \
+	func(is_geminilake); \
 	func(is_kabylake); \
 	func(is_alpha_support); \
 	/* Keep has_* in alphabetical order */ \
@@ -2432,6 +2433,7 @@  struct drm_i915_cmd_table {
 #define IS_BROADWELL(dev_priv)	((dev_priv)->info.is_broadwell)
 #define IS_SKYLAKE(dev_priv)	((dev_priv)->info.is_skylake)
 #define IS_BROXTON(dev_priv)	((dev_priv)->info.is_broxton)
+#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.is_geminilake)
 #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.is_kabylake)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f8b93c1..2c9645f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -372,6 +372,13 @@  static const struct intel_device_info intel_broxton_info = {
 	.ddb_size = 512,
 };
 
+static const struct intel_device_info intel_geminilake_info = {
+	.is_alpha_support = 1,
+	.is_geminilake = 1,
+	GEN9_LP_FEATURES,
+	.ddb_size = 1024,
+};
+
 static const struct intel_device_info intel_kabylake_info = {
 	BDW_FEATURES,
 	.is_kabylake = 1,