| Message ID | 1479305104-17049-1-git-send-email-min.he@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 2016.11.16 22:05:04 +0800, Min He wrote: > For a singl_port_submission context, it can only be submitted to port 0, > and there shouldn't be any other context in port 1 at the same time. This > is required by GVT-g context to have an opportunity to save/restore some > non-hw context render registers. > This patch is to implement the correct logic in execlists_dequeue. > > v2: optimized code by following Chris's advice, and added more comments to > explain the patch. > v3: followed the coding style. > > Signed-off-by: Min He <min.he@intel.com> > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> > --- Hi, Min, like Daniel said not need to add my s-o-b. > drivers/gpu/drm/i915/intel_lrc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index f50feaa..b2c0d50 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -499,7 +499,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > * context (even though a different request) to > * the second port. > */ > - if (ctx_single_port_submission(cursor->ctx)) > + if (ctx_single_port_submission(last->ctx) || > + ctx_single_port_submission(cursor->ctx)) > break; > > GEM_BUG_ON(last->ctx == cursor->ctx); > -- > 1.9.1 > Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
On Wed, Nov 16, 2016 at 10:05:04PM +0800, Min He wrote: > For a singl_port_submission context, it can only be submitted to port 0, > and there shouldn't be any other context in port 1 at the same time. This > is required by GVT-g context to have an opportunity to save/restore some > non-hw context render registers. This statement is not true. It has the opportunity to modify the GVT context if a non-GVT context was in port 0 or port 1. > This patch is to implement the correct logic in execlists_dequeue. I object. This is not the correct logic here, but to workaround a failure in GVT. Any way pushed until GVT is fixed. -Chris
> -----Original Message----- > From: Chris Wilson [mailto:chris@chris-wilson.co.uk] > Sent: Thursday, November 17, 2016 4:01 PM > To: He, Min <min.he@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: fix the dequeue logic for > single_port_submission context > > On Wed, Nov 16, 2016 at 10:05:04PM +0800, Min He wrote: > > For a singl_port_submission context, it can only be submitted to port 0, > > and there shouldn't be any other context in port 1 at the same time. This > > is required by GVT-g context to have an opportunity to save/restore some > > non-hw context render registers. > > This statement is not true. It has the opportunity to modify the GVT > context if a non-GVT context was in port 0 or port 1. If a non-GVT context is in port 0, and a GVT context in port 1, after non-GVT context completes, GPU will switch to GVT context directly, and we will lose the opportunity to save the non-GVT context registers and restore GVT context registers. So non-GVT context's register will impact GVT context. And vice versa. > > > This patch is to implement the correct logic in execlists_dequeue. > > I object. This is not the correct logic here, but to workaround a > failure in GVT. > > Any way pushed until GVT is fixed. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index f50feaa..b2c0d50 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -499,7 +499,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * context (even though a different request) to * the second port. */ - if (ctx_single_port_submission(cursor->ctx)) + if (ctx_single_port_submission(last->ctx) || + ctx_single_port_submission(cursor->ctx)) break; GEM_BUG_ON(last->ctx == cursor->ctx);