From patchwork Fri Nov 18 02:03:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 9435649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0E5A160471 for ; Fri, 18 Nov 2016 02:04:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F36F8296F6 for ; Fri, 18 Nov 2016 02:04:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E765C29731; Fri, 18 Nov 2016 02:04:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 17065296F6 for ; Fri, 18 Nov 2016 02:04:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3563B6E308; Fri, 18 Nov 2016 02:04:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 501706E308; Fri, 18 Nov 2016 02:04:32 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP; 17 Nov 2016 18:04:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.31,655,1473145200"; d="scan'208"; a="1060926624" Received: from nuc-skylake.jf.intel.com ([10.54.75.23]) by orsmga001.jf.intel.com with ESMTP; 17 Nov 2016 18:04:32 -0800 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Thu, 17 Nov 2016 18:03:47 -0800 Message-Id: <1479434628-2373-3-git-send-email-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1479434628-2373-1-git-send-email-dhinakaran.pandiyan@intel.com> References: <1479434628-2373-1-git-send-email-dhinakaran.pandiyan@intel.com> Cc: daniel.vetter@ffwll.ch, dri-devel@lists.freedesktop.org, Dhinakaran Pandiyan Subject: [Intel-gfx] [PATCH 2/3] drm/dp/mst: Calculate total link bandwidth instead of hardcoding it X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The total or the nominal link bandwidth, which we save in terms of PBN, is a factor of link rate and lane count. But, currently we hardcode it to 2560 PBN. This results in incorrect computation of total slots. E.g, 2 lane HBR2 configuration and 4k@60Hz, 24bpp mode nominal link bw = 1080 MBps = 1280PBN = 64 slots required bw 533.25 MHz*3 = 1599.75 MBps or 1896 PBN with +0.6% margin = 1907.376 PBN = 96 slots This is greater than the max. possible value of 64 slots. But, we incorrectly compute available slots as 2560 PBN = 128 slots and don't return error. So, let's fix this by calculating the total link bandwidth as link bw (PBN) = BW per time slot(PBN) * max. time slots , where max. time slots is 64 Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/drm_dp_mst_topology.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 04e4571..26dfd99 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -2038,9 +2038,8 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms ret = -EINVAL; goto out_unlock; } - - mgr->total_pbn = 2560; - mgr->total_slots = DIV_ROUND_UP(mgr->total_pbn, mgr->pbn_div); + mgr->total_pbn = 64 * mgr->pbn_div; + mgr->total_slots = 64; mgr->avail_slots = mgr->total_slots; /* add initial branch device at LCT 1 */