From patchwork Tue Nov 22 21:39:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 9442251 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AAA8A60235 for ; Tue, 22 Nov 2016 21:37:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B1801FEBD for ; Tue, 22 Nov 2016 21:37:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8FBE51FFD7; Tue, 22 Nov 2016 21:37:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 307081FEBD for ; Tue, 22 Nov 2016 21:37:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1DADE6E6A7; Tue, 22 Nov 2016 21:37:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id C70DB6E698; Tue, 22 Nov 2016 21:37:14 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP; 22 Nov 2016 13:37:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,682,1473145200"; d="scan'208";a="8113002" Received: from manasi-otcmedia.jf.intel.com ([10.7.199.175]) by orsmga002.jf.intel.com with ESMTP; 22 Nov 2016 13:37:13 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 22 Nov 2016 13:39:26 -0800 Message-Id: <1479850766-32748-6-git-send-email-manasi.d.navare@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479850766-32748-1-git-send-email-manasi.d.navare@intel.com> References: <1479850766-32748-1-git-send-email-manasi.d.navare@intel.com> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Add support for DP Video pattern compliance tests X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The intel_dp_autotest_video_pattern() function gets invoked through the compliance test handler on a HPD short pulse if the test type is set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers reads to read the requested test pattern, video pattern resolution, frame rate and bits per color value. The results of this analysis are handed off to userspace so that the userspace app can set the video pattern mode appropriately for the test result/response. The compliance_test_active flag is set at the end of the individual test handling functions. This is so that the kernel-side operations can be completed without the risk of interruption from the userspace app that is polling on that flag. Signed-off-by: Manasi Navare Cc: Jani Nikula Cc: Daniel Vetter Cc: Ville Syrjala --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++- drivers/gpu/drm/i915/intel_dp.c | 68 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 9 +++++ 3 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 3799a12..b048a0e 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4545,7 +4545,19 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data) if (connector->status == connector_status_connected && connector->encoder != NULL) { intel_dp = enc_to_intel_dp(connector->encoder); - seq_printf(m, "%lx", intel_dp->compliance_test_data); + if (intel_dp->compliance_test_type == + DP_TEST_LINK_EDID_READ) + seq_printf(m, "%lx", + intel_dp->compliance_test_data); + else if (intel_dp->compliance_test_type == + DP_TEST_LINK_VIDEO_PATTERN) { + seq_printf(m, "hdisplay: %d\n", + intel_dp->test_data.hdisplay); + seq_printf(m, "vdisplay: %d\n", + intel_dp->test_data.vdisplay); + seq_printf(m, "bpc: %u\n", + intel_dp->test_data.bpc); + } } else seq_puts(m, "0"); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f93e130..784f86e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -28,8 +28,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -3868,7 +3870,73 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) { uint8_t test_result = DP_TEST_NAK; + uint8_t test_pattern; + uint16_t test_misc; + __be16 h_width, v_height; + int status = 0; + + /* Read the TEST_PATTERN (DP CTS 3.1.5) */ + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN, + &test_pattern, 1); + if (status <= 0) { + DRM_DEBUG_KMS("Could not read test pattern from " + "reference sink\n"); + return 0; + } + if (test_pattern != DP_COLOR_RAMP) + return test_result; + intel_dp->test_data.video_pattern = test_pattern; + + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH, + &h_width, 2); + if (status <= 0) { + DRM_DEBUG_KMS("Could not read H Width from " + "reference sink\n"); + return 0; + } + intel_dp->test_data.hdisplay = be16_to_cpu(h_width); + + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT, + &v_height, 2); + if (status <= 0) { + DRM_DEBUG_KMS("Could not read V Height from " + "reference sink\n"); + return 0; + } + intel_dp->test_data.vdisplay = be16_to_cpu(v_height); + + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC, + &test_misc, 1); + if (status <= 0) { + DRM_DEBUG_KMS("Could not read TEST MISC from " + "reference sink\n"); + return 0; + } + if (((test_misc & DP_TEST_COLOR_FORMAT_MASK) >> DP_TEST_MISC_BIT_1) != + DP_VIDEO_PATTERN_RGB_FORMAT) + return test_result; + if (((test_misc & DP_TEST_DYNAMIC_RANGE_MASK) >> DP_TEST_MISC_BIT_3) != + DP_VIDEO_PATTERN_VESA) + return test_result; + switch ((test_misc & DP_TEST_BIT_DEPTH_MASK) >> DP_TEST_MISC_BIT_5) { + case 0: + intel_dp->compliance_force_bpc = 6; + intel_dp->test_data.bpc = 6; + break; + case 1: + intel_dp->compliance_force_bpc = 8; + intel_dp->test_data.bpc = 8; + break; + default: + return test_result; + } + /* Set test active flag here so userspace doesn't interrupt things */ + intel_dp->compliance_test_active = 1; + + test_result = DP_TEST_ACK; + return test_result; + } static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3eb428e..ff4431e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -880,6 +880,12 @@ struct intel_dp_desc { u8 sw_minor_rev; } __packed; +struct compliance_test_data { + uint8_t video_pattern; + uint16_t hdisplay, vdisplay; + uint8_t bpc; +}; + struct intel_dp { i915_reg_t output_reg; i915_reg_t aux_ch_ctl_reg; @@ -961,6 +967,9 @@ struct intel_dp { u8 compliance_test_lane_count; u8 compliance_test_link_rate; unsigned long compliance_force_bpc; /* 0 for default or bpc to use */ + struct compliance_test_data test_data; /* a structure to hold all dp + * compliance test data + */ }; struct intel_lspcon {