@@ -336,4 +336,8 @@
INTEL_KBL_GT3_IDS(info), \
INTEL_KBL_GT4_IDS(info)
+#define INTEL_GLK_IDS(info) \
+ INTEL_VGA_DEVICE(0x3184, info), \
+ INTEL_VGA_DEVICE(0x3185, info)
+
#endif /* _I915_PCIIDS_H */
@@ -134,6 +134,10 @@ static const struct intel_device_info intel_kabylake_info = {
.gen = 0112,
};
+static const struct intel_device_info intel_geminilake_info = {
+ .gen = 0113,
+};
+
static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_I810, "i810"},
{PCI_CHIP_I810_DC100, "i810-dc100"},
@@ -335,6 +339,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_KBL_IDS(&intel_kabylake_info),
+ INTEL_GLK_IDS(&intel_geminilake_info),
+
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
#endif
@@ -240,6 +240,11 @@ static const struct gt_info kbl_gt_info = {
.urb = { .max_vs_entries = 960 },
};
+static const struct gt_info glk_gt_info = {
+ .name = "Geminilake (gen9)",
+ .urb = { .max_vs_entries = 320 },
+};
+
static bool is_skl(struct sna *sna)
{
return sna->kgem.gen == 0110;
@@ -255,6 +260,11 @@ static bool is_kbl(struct sna *sna)
return sna->kgem.gen == 0112;
}
+static bool is_glk(struct sna *sna)
+{
+ return sna->kgem.gen == 0113;
+}
+
static inline bool too_large(int width, int height)
{
@@ -4012,6 +4022,8 @@ static bool gen9_render_setup(struct sna *sna)
state->info = &bxt_gt_info;
if (is_kbl(sna))
state->info = &kbl_gt_info;
+ if (is_glk(sna))
+ state->info = &glk_gt_info;
sna_static_stream_init(&general);
Same ids from kernel's commit 8363e3c3947d0e22955f94a6a87e4f17ce5087b4 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Thu Nov 10 17:23:08 2016 +0200 drm/i915/glk: Add Geminilake PCI IDs Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- src/i915_pciids.h | 4 ++++ src/intel_module.c | 6 ++++++ src/sna/gen9_render.c | 12 ++++++++++++ 3 files changed, 22 insertions(+)