From patchwork Mon Jan 2 12:54:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chauhan, Madhav" X-Patchwork-Id: 9493433 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D95BA62AB4 for ; Mon, 2 Jan 2017 12:54:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CDA151FF27 for ; Mon, 2 Jan 2017 12:54:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C29AB2015F; Mon, 2 Jan 2017 12:54:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3F65A1FF27 for ; Mon, 2 Jan 2017 12:54:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AAA3389E69; Mon, 2 Jan 2017 12:54:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 768F389E69 for ; Mon, 2 Jan 2017 12:54:37 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP; 02 Jan 2017 04:54:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,432,1477983600"; d="scan'208";a="208804911" Received: from unknown (HELO MCHAUHANVM.gar.corp.intel.com) ([10.109.67.20]) by fmsmga004.fm.intel.com with ESMTP; 02 Jan 2017 04:54:33 -0800 From: Madhav Chauhan To: intel-gfx@lists.freedesktop.org Date: Mon, 2 Jan 2017 07:54:22 -0500 Message-Id: <1483361668-2095-2-git-send-email-madhav.chauhan@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1483361668-2095-1-git-send-email-madhav.chauhan@intel.com> References: <1483361668-2095-1-git-send-email-madhav.chauhan@intel.com> Cc: ander.conselvan.de.oliveira@intel.com, ville.syrjala@intel.com, jani.nikula@intel.com, shobhit.kumar@intel.com, Deepak M Subject: [Intel-gfx] [GLK MIPI DSI V3 1/7] drm/i915/glk: Program dphy param reg for GLK X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Deepak M For GEMINILAKE, dphy param reg values are programmed in terms of HS byte clock count while for legacy platforms in terms of HS ddr clk count. Signed-off-by: Deepak M Signed-off-by: Madhav Chauhan --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 33 +++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index 8f683b8..8059cbb 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -695,16 +695,26 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) /* count values in UI = (ns value) * (bitrate / (2 * 10^6)) * * Since txddrclkhs_i is 2xUI, all the count values programmed in - * DPHY param register are divided by 2 + * DPHY param register are divided by 2 except GEMINILAKE where it is + * programmed in terms of HS byte clock so divided by 8 * * prepare count */ ths_prepare_ns = max(mipi_config->ths_prepare, mipi_config->tclk_prepare); - prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); + if (IS_GEMINILAKE(dev_priv)) + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 8); + else + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); /* exit zero count */ - exit_zero_cnt = DIV_ROUND_UP( + if (IS_GEMINILAKE(dev_priv)) + exit_zero_cnt = DIV_ROUND_UP( + (ths_prepare_hszero - ths_prepare_ns) * ui_den, + ui_num * 8 + ); + else + exit_zero_cnt = DIV_ROUND_UP( (ths_prepare_hszero - ths_prepare_ns) * ui_den, ui_num * 2 ); @@ -719,13 +729,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) exit_zero_cnt += 1; /* clk zero count */ - clk_zero_cnt = DIV_ROUND_UP( - (tclk_prepare_clkzero - ths_prepare_ns) - * ui_den, 2 * ui_num); + if (IS_GEMINILAKE(dev_priv)) + clk_zero_cnt = DIV_ROUND_UP( + (tclk_prepare_clkzero - ths_prepare_ns) + * ui_den, 8 * ui_num); + else + clk_zero_cnt = DIV_ROUND_UP( + (tclk_prepare_clkzero - ths_prepare_ns) + * ui_den, 2 * ui_num); /* trail count */ tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); - trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); + + if (IS_GEMINILAKE(dev_priv)) + trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 * ui_num); + else + trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); if (prepare_cnt > PREPARE_CNT_MAX || exit_zero_cnt > EXIT_ZERO_CNT_MAX ||