| Message ID | 1483720352-24761-1-git-send-email-vathsala.nagaraju@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> On Fri, 2017-01-06 at 22:02 +0530, vathsala nagaraju wrote: > Reports live state of PSR2 form PSR2_STATUS register. > bit field 31:28 gives the live state of PSR2. > It can be used to check if system is in deep sleep, > selective update or selective update standby. > During video play back, we can use this to check > if system is entering SU mode or not. > when system is in idle state, DEEP_SLEEP(8) must be entered. > When video playback is happening, system must be in > SLEEP(3 / selective update) or SU_STANDBY( 6 / selective update standby) > > v2: (Rodrigo) > - Remove EDP_PSR2_STATUS_TG_ON=a ,instead use ARRAY_SIZE > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Jim Bride <jim.bride@linux.intel.com> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> > Signed-off-by: Patil Deepti <deepti.patil@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 9d7b5a8..ec9013e 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2606,6 +2606,30 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > > seq_printf(m, "Performance_Counter: %u\n", psrperf); > } > + if (dev_priv->psr.psr2_support) { > + static const char * const live_status[] = { > + "IDLE", > + "CAPTURE", > + "CAPTURE_FS", > + "SLEEP", > + "BUFON_FW", > + "ML_UP", > + "SU_STANDBY", > + "FAST_SLEEP", > + "DEEP_SLEEP", > + "BUF_ON", > + "TG_ON" }; > + u8 pos = (I915_READ(EDP_PSR2_STATUS_CTL) & > + EDP_PSR2_STATUS_STATE_MASK) >> > + EDP_PSR2_STATUS_STATE_SHIFT; > + > + seq_printf(m, "PSR2_STATUS_EDP: %x\n", > + I915_READ(EDP_PSR2_STATUS_CTL)); > + > + if (pos < ARRAY_SIZE(live_status)) > + seq_printf(m, "PSR2 live state %s\n", > + live_status[pos]); > + } > mutex_unlock(&dev_priv->psr.lock); > > intel_runtime_pm_put(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 272a283..65fffc5 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3621,6 +3621,7 @@ enum { > > #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) > #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) > +#define EDP_PSR2_STATUS_STATE_SHIFT 28 > > /* VGA port control */ > #define ADPA _MMIO(0x61100)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9d7b5a8..ec9013e 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2606,6 +2606,30 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "Performance_Counter: %u\n", psrperf); } + if (dev_priv->psr.psr2_support) { + static const char * const live_status[] = { + "IDLE", + "CAPTURE", + "CAPTURE_FS", + "SLEEP", + "BUFON_FW", + "ML_UP", + "SU_STANDBY", + "FAST_SLEEP", + "DEEP_SLEEP", + "BUF_ON", + "TG_ON" }; + u8 pos = (I915_READ(EDP_PSR2_STATUS_CTL) & + EDP_PSR2_STATUS_STATE_MASK) >> + EDP_PSR2_STATUS_STATE_SHIFT; + + seq_printf(m, "PSR2_STATUS_EDP: %x\n", + I915_READ(EDP_PSR2_STATUS_CTL)); + + if (pos < ARRAY_SIZE(live_status)) + seq_printf(m, "PSR2 live state %s\n", + live_status[pos]); + } mutex_unlock(&dev_priv->psr.lock); intel_runtime_pm_put(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 272a283..65fffc5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3621,6 +3621,7 @@ enum { #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) +#define EDP_PSR2_STATUS_STATE_SHIFT 28 /* VGA port control */ #define ADPA _MMIO(0x61100)