From patchwork Fri Feb 17 13:22:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 9579795 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 53983600C5 for ; Fri, 17 Feb 2017 13:22:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4352F286C7 for ; Fri, 17 Feb 2017 13:22:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 383F7286D6; Fri, 17 Feb 2017 13:22:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D7F79286C7 for ; Fri, 17 Feb 2017 13:22:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DF0D6ECF1; Fri, 17 Feb 2017 13:22:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEC206ECFC for ; Fri, 17 Feb 2017 13:22:19 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Feb 2017 05:22:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,171,1484035200"; d="scan'208";a="67021022" Received: from przanoni-mobl.amr.corp.intel.com ([10.254.183.49]) by fmsmga006.fm.intel.com with ESMTP; 17 Feb 2017 05:22:18 -0800 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Feb 2017 11:22:05 -0200 Message-Id: <1487337727-9813-3-git-send-email-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487337727-9813-1-git-send-email-paulo.r.zanoni@intel.com> References: <1487337727-9813-1-git-send-email-paulo.r.zanoni@intel.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 2/4] drm/i915: add intel_calc_cdclk() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Each x_modeset_calc_cdclk() has to do the same platform checks twice, so extract them to a single function. This way, the platform checks are all in the same place, and the platform-common code gets rid of all the platform-specific checks, which IMHO makes the code easier to read. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_cdclk.c | 84 ++++++++++++++++++++------------------ 1 file changed, 45 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index d505ff1..6efc5f4 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1496,6 +1496,47 @@ static int intel_max_pixel_rate(struct drm_atomic_state *state) return max_pixel_rate; } +static void intel_calc_cdclk(struct intel_atomic_state *state, int max_pixclk, + int *cdclk, int *vco) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + + switch (INTEL_INFO(dev_priv)->platform) { + case INTEL_VALLEYVIEW: + case INTEL_CHERRYVIEW: + *cdclk = vlv_calc_cdclk(dev_priv, max_pixclk); + break; + case INTEL_BROADWELL: + /* + * FIXME: should also account for plane ratio once 64bpp pixel + * formats are supported. + */ + *cdclk = bdw_calc_cdclk(max_pixclk); + break; + case INTEL_SKYLAKE: + case INTEL_KABYLAKE: + /* + * FIXME: should also account for plane ratio once 64bpp pixel + * formats are supported. + */ + *vco = state->cdclk.logical.vco; + if (!*vco) + *vco = dev_priv->skl_preferred_vco_freq; + *cdclk = skl_calc_cdclk(max_pixclk, *vco); + break; + case INTEL_BROXTON: + *cdclk = bxt_calc_cdclk(max_pixclk); + *vco = bxt_de_pll_vco(dev_priv, *cdclk); + break; + case INTEL_GEMINILAKE: + *cdclk = glk_calc_cdclk(max_pixclk); + *vco = glk_de_pll_vco(dev_priv, *cdclk); + break; + default: + MISSING_CASE(INTEL_INFO(dev_priv)->platform); + } +} + static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->dev); @@ -1503,14 +1544,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) int max_pixclk = intel_max_pixel_rate(state); int cdclk; - /* - * FIXME: Broadwell should also account for plane ratio once 64bpp pixel - * formats are supported. - */ - if (IS_BROADWELL(dev_priv)) - cdclk = bdw_calc_cdclk(max_pixclk); - else - cdclk = vlv_calc_cdclk(dev_priv, max_pixclk); + intel_calc_cdclk(intel_state, max_pixclk, &cdclk, NULL); if (cdclk > dev_priv->max_cdclk_freq) { DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", @@ -1521,11 +1555,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) intel_state->cdclk.logical.cdclk = cdclk; if (!intel_state->active_crtcs) { - if (IS_BROADWELL(dev_priv)) - cdclk = bdw_calc_cdclk(0); - else - cdclk = vlv_calc_cdclk(dev_priv, 0); - + intel_calc_cdclk(intel_state, 0, &cdclk, NULL); intel_state->cdclk.actual.cdclk = cdclk; } else { intel_state->cdclk.actual = intel_state->cdclk.logical; @@ -1541,22 +1571,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) int max_pixclk = intel_max_pixel_rate(state); int cdclk, vco; - /* - * FIXME: Skylake/Kabylake should also account for plane ratio once - * 64bpp pixel formats are supported. - */ - if (IS_GEMINILAKE(dev_priv)) { - cdclk = glk_calc_cdclk(max_pixclk); - vco = glk_de_pll_vco(dev_priv, cdclk); - } else if (IS_BROXTON(dev_priv)) { - cdclk = bxt_calc_cdclk(max_pixclk); - vco = bxt_de_pll_vco(dev_priv, cdclk); - } else { - vco = intel_state->cdclk.logical.vco; - if (!vco) - vco = dev_priv->skl_preferred_vco_freq; - cdclk = skl_calc_cdclk(max_pixclk, vco); - } + intel_calc_cdclk(intel_state, max_pixclk, &cdclk, &vco); if (cdclk > dev_priv->max_cdclk_freq) { DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", @@ -1568,16 +1583,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) intel_state->cdclk.logical.cdclk = cdclk; if (!intel_state->active_crtcs) { - if (IS_GEMINILAKE(dev_priv)) { - cdclk = glk_calc_cdclk(0); - vco = glk_de_pll_vco(dev_priv, cdclk); - } else if (IS_BROXTON(dev_priv)) { - cdclk = bxt_calc_cdclk(0); - vco = bxt_de_pll_vco(dev_priv, cdclk); - } else { - cdclk = skl_calc_cdclk(0, vco); - } - + intel_calc_cdclk(intel_state, 0, &cdclk, &vco); intel_state->cdclk.actual.vco = vco; intel_state->cdclk.actual.cdclk = cdclk; } else {