From patchwork Mon Feb 20 20:00:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 9583565 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6FBF4604A0 for ; Mon, 20 Feb 2017 20:01:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 63D3728885 for ; Mon, 20 Feb 2017 20:01:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 58B5528887; Mon, 20 Feb 2017 20:01:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E9DB928885 for ; Mon, 20 Feb 2017 20:01:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D8256E532; Mon, 20 Feb 2017 20:01:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4FF6B6E532 for ; Mon, 20 Feb 2017 20:00:59 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP; 20 Feb 2017 12:00:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.35,187,1484035200"; d="scan'208"; a="1132505633" Received: from przanoni-mobl.amr.corp.intel.com ([10.254.179.244]) by fmsmga002.fm.intel.com with ESMTP; 20 Feb 2017 12:00:57 -0800 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2017 17:00:42 -0300 Message-Id: <1487620842-22893-4-git-send-email-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487620842-22893-1-git-send-email-paulo.r.zanoni@intel.com> References: <1487620842-22893-1-git-send-email-paulo.r.zanoni@intel.com> MIME-Version: 1.0 Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 3/3] drm/i915: reorganize the get_cdclk assignment X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Possible problems of the current if-ladder: - It's a huge if ladder with almost a different check for each of our platforms. - It mixes 3 different types of checks: IS_GENX, IS_PLATFORM and IS_GROUP_OF_PLATFORMS. - As demonstrated by the recent IS_G4X commit, it's not easy to be sure if a platform down on the list isn't also checked earlier. - As demonstrated by the WARN at the end, it's not easy to be sure if we're actually checking for every single platform. Possible advantages of the new switch statement: - It may be easier for the compiler to optimize stuff (I didn't check this), especially since the values are labels of an enum. - The compiler will tell us in case we miss some platform. - All platforms are explicitly there instead of maybe hidden in some check for a certain group of platforms such as IS_GEN9_BC. Possible disadvantages with the new code: - A few lines bigger. v2: Don't unsort the list. Now the list almost matches the enum definition, with the exception of CHV, KBL and GLK, which are listed along their predecessors (Ville). Cc: Ville Syrjälä Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_cdclk.c | 105 +++++++++++++++++++++++-------------- 1 file changed, 66 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 942adf0..e1921fe7 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1762,49 +1762,76 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.calc_cdclk_state = skl_calc_cdclk_state; } - if (IS_GEN9_BC(dev_priv)) - dev_priv->display.get_cdclk = skl_get_cdclk; - else if (IS_GEN9_LP(dev_priv)) - dev_priv->display.get_cdclk = bxt_get_cdclk; - else if (IS_BROADWELL(dev_priv)) - dev_priv->display.get_cdclk = bdw_get_cdclk; - else if (IS_HASWELL(dev_priv)) - dev_priv->display.get_cdclk = hsw_get_cdclk; - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - dev_priv->display.get_cdclk = vlv_get_cdclk; - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + switch (INTEL_INFO(dev_priv)->platform) { + case INTEL_PLATFORM_UNINITIALIZED: + MISSING_CASE(INTEL_INFO(dev_priv)->platform); + /* Fall through. */ + case INTEL_I830: + dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; + break; + case INTEL_I845G: + dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; + break; + case INTEL_I85X: + dev_priv->display.get_cdclk = i85x_get_cdclk; + break; + case INTEL_I865G: + dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; + break; + case INTEL_I915G: + dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; + break; + case INTEL_I915GM: + dev_priv->display.get_cdclk = i915gm_get_cdclk; + break; + case INTEL_I945G: dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; - else if (IS_GEN5(dev_priv)) - dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; - else if (IS_GM45(dev_priv)) - dev_priv->display.get_cdclk = gm45_get_cdclk; - else if (IS_G45(dev_priv)) + break; + case INTEL_I945GM: + dev_priv->display.get_cdclk = i945gm_get_cdclk; + break; + case INTEL_G33: dev_priv->display.get_cdclk = g33_get_cdclk; - else if (IS_I965GM(dev_priv)) - dev_priv->display.get_cdclk = i965gm_get_cdclk; - else if (IS_I965G(dev_priv)) - dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; - else if (IS_PINEVIEW(dev_priv)) + break; + case INTEL_PINEVIEW: dev_priv->display.get_cdclk = pnv_get_cdclk; - else if (IS_G33(dev_priv)) + break; + case INTEL_I965G: + dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; + break; + case INTEL_I965GM: + dev_priv->display.get_cdclk = i965gm_get_cdclk; + break; + case INTEL_G45: dev_priv->display.get_cdclk = g33_get_cdclk; - else if (IS_I945GM(dev_priv)) - dev_priv->display.get_cdclk = i945gm_get_cdclk; - else if (IS_I945G(dev_priv)) + break; + case INTEL_GM45: + dev_priv->display.get_cdclk = gm45_get_cdclk; + break; + case INTEL_IRONLAKE: + dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; + break; + case INTEL_SANDYBRIDGE: + case INTEL_IVYBRIDGE: dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; - else if (IS_I915GM(dev_priv)) - dev_priv->display.get_cdclk = i915gm_get_cdclk; - else if (IS_I915G(dev_priv)) - dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; - else if (IS_I865G(dev_priv)) - dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; - else if (IS_I85X(dev_priv)) - dev_priv->display.get_cdclk = i85x_get_cdclk; - else if (IS_I845G(dev_priv)) - dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; - else { /* 830 */ - WARN(!IS_I830(dev_priv), - "Unknown platform. Assuming 133 MHz CDCLK\n"); - dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; + break; + case INTEL_VALLEYVIEW: + case INTEL_CHERRYVIEW: + dev_priv->display.get_cdclk = vlv_get_cdclk; + break; + case INTEL_HASWELL: + dev_priv->display.get_cdclk = hsw_get_cdclk; + break; + case INTEL_BROADWELL: + dev_priv->display.get_cdclk = bdw_get_cdclk; + break; + case INTEL_SKYLAKE: + case INTEL_KABYLAKE: + dev_priv->display.get_cdclk = skl_get_cdclk; + break; + case INTEL_BROXTON: + case INTEL_GEMINILAKE: + dev_priv->display.get_cdclk = bxt_get_cdclk; + break; } }