| Message ID | 1487812767-12422-1-git-send-email-daniele.ceraolospurio@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Feb 22, 2017 at 05:19:27PM -0800, Daniele Ceraolo Spurio wrote: > The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV > register the GuC can use to restore the provided whitelist when an > engine reset via GuC (which we still don't support) is triggered. > > We're currently adding the mmio_base of the engine to the absolute > address of the RCS version of the register, which results in the wrong > offset. Fix it by using the definition we already have instead of > re-defining it in the GuC FW header. > > Also add a comment to avoid future issues with FORCE_TO_NONPRIV > registers, which are also used by the workaround framework. > > v2: improve comment (Michal), move comment about save/restore because it > is not related to the mmio_white_list field. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Michał Winiarski <michal.winiarski@intel.com> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> > Cc: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> -Michał > --- > drivers/gpu/drm/i915/i915_guc_submission.c | 11 +++++++++-- > drivers/gpu/drm/i915/intel_guc_fwif.h | 1 - > 2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index beec88a..c689fe5 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -852,10 +852,17 @@ static void guc_addon_create(struct intel_guc *guc) for_each_engine(engine, dev_priv, id) { reg_state->mmio_white_list[engine->guc_id].mmio_start = - engine->mmio_base + GUC_MMIO_WHITE_LIST_START; + i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(engine->mmio_base, 0)); - /* Nothing to be saved or restored for now. */ + /* + * Note: if the GuC whitelist management is enabled, the values + * should be filled using the workaround framework to avoid + * inconsistencies with the handling of FORCE_TO_NONPRIV + * registers. + */ reg_state->mmio_white_list[engine->guc_id].count = 0; + + /* Nothing to be saved or restored for now. */ } ads->reg_state_addr = ads->scheduler_policies + diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 25691f0..da7dcac 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -386,7 +386,6 @@ struct guc_policies { #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 #define GUC_REGSET_MAX_REGISTERS 25 -#define GUC_MMIO_WHITE_LIST_START 0x24d0 #define GUC_MMIO_WHITE_LIST_MAX 12 #define GUC_S3_SAVE_SPACE_PAGES 10
The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV register the GuC can use to restore the provided whitelist when an engine reset via GuC (which we still don't support) is triggered. We're currently adding the mmio_base of the engine to the absolute address of the RCS version of the register, which results in the wrong offset. Fix it by using the definition we already have instead of re-defining it in the GuC FW header. Also add a comment to avoid future issues with FORCE_TO_NONPRIV registers, which are also used by the workaround framework. v2: improve comment (Michal), move comment about save/restore because it is not related to the mmio_white_list field. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> --- drivers/gpu/drm/i915/i915_guc_submission.c | 11 +++++++++-- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 - 2 files changed, 9 insertions(+), 3 deletions(-)