From patchwork Wed Mar 1 02:57:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 9597345 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7EAA3604AA for ; Wed, 1 Mar 2017 03:04:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 799762022B for ; Wed, 1 Mar 2017 03:04:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6DE592842B; Wed, 1 Mar 2017 03:04:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 70BD92842B for ; Wed, 1 Mar 2017 03:04:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CF4D6E878; Wed, 1 Mar 2017 03:04:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 03DA86E878 for ; Wed, 1 Mar 2017 02:59:01 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Feb 2017 18:59:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,223,1484035200"; d="scan'208";a="939229748" Received: from nuc-skylake.jf.intel.com ([10.54.75.136]) by orsmga003.jf.intel.com with ESMTP; 28 Feb 2017 18:59:00 -0800 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Tue, 28 Feb 2017 18:57:18 -0800 Message-Id: <1488337038-2906-2-git-send-email-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488337038-2906-1-git-send-email-dhinakaran.pandiyan@intel.com> References: <1488337038-2906-1-git-send-email-dhinakaran.pandiyan@intel.com> Cc: Ander Conselvan de Oliveira , Dhinakaran Pandiyan Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Implement BXT and GLK cdclk restriction based on Azalia BCLK X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP According to BSpec, "The CD clock frequency must be at least twice the frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by default. BXT and GLK both have cdclk frequencies that are less han 192 MHz, so apply the check conditionally for these platforms. Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_cdclk.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 8fc0f72..89027fa 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1444,6 +1444,8 @@ static int intel_min_cdclk(struct drm_atomic_state *state) struct intel_crtc_state *crtc_state; crtc_state = to_intel_crtc_state(cstate); + if (!crtc_state->has_audio) + continue; /* According to BSpec, "Do not use DisplayPort with CDCLK less * than 432 MHz, audio enabled, port width x4, and link rate @@ -1452,7 +1454,6 @@ static int intel_min_cdclk(struct drm_atomic_state *state) * for GLK is at 316.8 MHz */ if (intel_crtc_has_dp_encoder(crtc_state) && - crtc_state->has_audio && crtc_state->port_clock >= 540000 && crtc_state->lane_count == 4) { if (IS_GEMINILAKE(dev_priv)) @@ -1460,6 +1461,13 @@ static int intel_min_cdclk(struct drm_atomic_state *state) else if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) min_cdclk = 432000; } + + /* According to BSpec, "The CD clock frequency must be at least + * twice the frequency of the Azalia BCLK." and BCLK is 96 MHz + * by default. + */ + if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) + min_cdclk = max(min_cdclk, 2 * 96000); } return min_cdclk;