From patchwork Thu Mar 16 06:20:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sourab.gupta@intel.com X-Patchwork-Id: 9627279 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 88204604A9 for ; Thu, 16 Mar 2017 06:18:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 780FF28543 for ; Thu, 16 Mar 2017 06:18:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6CF08285EF; Thu, 16 Mar 2017 06:18:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 13B2D28543 for ; Thu, 16 Mar 2017 06:18:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A8A386E9F1; Thu, 16 Mar 2017 06:18:12 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 082996E9F1 for ; Thu, 16 Mar 2017 06:18:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1489645088; x=1521181088; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=FPfDTPpesq4nbg4lZPcXLDc6fcCdJJuKwy+uLNeapCE=; b=pCUAHuU9CVWpJ8ZaQBjHNLflt6spo+vnd5m0mI8iuLl70qmbXo901WJB Ec7fvnwjpNtwd5faY9sNuxAm8Dn1Cw==; Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Mar 2017 23:18:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,170,1486454400"; d="scan'208";a="75987534" Received: from sourab-desktop.iind.intel.com ([10.223.82.140]) by orsmga005.jf.intel.com with ESMTP; 15 Mar 2017 23:18:06 -0700 From: sourab.gupta@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Mar 2017 11:50:08 +0530 Message-Id: <1489645211-25729-4-git-send-email-sourab.gupta@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489645211-25729-1-git-send-email-sourab.gupta@intel.com> References: <1489645211-25729-1-git-send-email-sourab.gupta@intel.com> Cc: Daniel Vetter , Sourab Gupta , Matthew Auld Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Support opening multiple concurrent perf streams X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Sourab Gupta This patch adds support for opening multiple concurrent perf streams for different gpu engines, while having the restriction to open only a single stream open for a particular gpu engine. This enables userspace client to open multiple streams, one per engine, at any time to capture sample data for multiple gpu engines. Signed-off-by: Sourab Gupta --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_perf.c | 41 ++++++++++++++++++++++------------------ 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 40ac362..c005ffa 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2547,7 +2547,7 @@ struct drm_i915_private { spinlock_t hook_lock; struct hrtimer poll_check_timer; - struct i915_perf_stream *exclusive_stream; + struct i915_perf_stream *engine_stream[I915_NUM_ENGINES]; wait_queue_head_t poll_wq[I915_NUM_ENGINES]; bool pollin[I915_NUM_ENGINES]; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index d3d934e..5437d08 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1382,7 +1382,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream, * switches since it's not-uncommon for periodic samples to * identify a switch before any 'context switch' report. */ - if (!dev_priv->perf.exclusive_stream->ctx || + if (!stream->ctx || dev_priv->perf.oa.specific_ctx_id == ctx_id || (dev_priv->perf.oa.oa_buffer.last_ctx_id == dev_priv->perf.oa.specific_ctx_id) || @@ -1391,7 +1391,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream, /* While filtering for a single context we avoid * leaking the IDs of other contexts. */ - if (dev_priv->perf.exclusive_stream->ctx && + if (stream->ctx && dev_priv->perf.oa.specific_ctx_id != ctx_id) { report32[2] = INVALID_CTX_ID; } @@ -2190,7 +2190,7 @@ static void i915_engine_stream_destroy(struct i915_perf_stream *stream) { struct drm_i915_private *dev_priv = stream->dev_priv; - if (WARN_ON(stream != dev_priv->perf.exclusive_stream)) + if (WARN_ON(stream != dev_priv->perf.engine_stream[stream->engine])) return; if (stream->using_oa) { @@ -2208,7 +2208,7 @@ static void i915_engine_stream_destroy(struct i915_perf_stream *stream) if (stream->cs_mode) free_command_stream_buf(dev_priv, stream->engine); - dev_priv->perf.exclusive_stream = NULL; + dev_priv->perf.engine_stream[stream->engine] = NULL; } static void gen7_init_oa_buffer(struct drm_i915_private *dev_priv) @@ -2755,10 +2755,10 @@ static void gen7_update_oacontrol_locked(struct drm_i915_private *dev_priv) { assert_spin_locked(&dev_priv->perf.hook_lock); - if (dev_priv->perf.exclusive_stream->state != + if (dev_priv->perf.engine_stream[RCS]->state != I915_PERF_STREAM_DISABLED) { struct i915_gem_context *ctx = - dev_priv->perf.exclusive_stream->ctx; + dev_priv->perf.engine_stream[RCS]->ctx; u32 ctx_id = dev_priv->perf.oa.specific_ctx_id; bool periodic = dev_priv->perf.oa.periodic; @@ -2931,8 +2931,9 @@ static int i915_engine_stream_init(struct i915_perf_stream *stream, * counter reports and marshal to the appropriate client * we currently only allow exclusive access */ - if (dev_priv->perf.exclusive_stream) { - DRM_DEBUG("I915 perf stream already in use\n"); + if (dev_priv->perf.engine_stream[props->engine]) { + DRM_DEBUG("I915 perf stream : %d already in use\n", + props->engine); return -EBUSY; } @@ -3120,7 +3121,7 @@ static int i915_engine_stream_init(struct i915_perf_stream *stream, } stream->ops = &i915_engine_stream_ops; - dev_priv->perf.exclusive_stream = stream; + dev_priv->perf.engine_stream[stream->engine] = stream; return 0; @@ -3343,24 +3344,28 @@ static ssize_t i915_perf_read(struct file *file, return ret; } -static enum hrtimer_restart poll_check_timer_cb(struct hrtimer *hrtimer) +static void wake_up_perf_streams(void *data, async_cookie_t cookie) { + struct drm_i915_private *dev_priv = data; struct i915_perf_stream *stream; - struct drm_i915_private *dev_priv = - container_of(hrtimer, typeof(*dev_priv), - perf.poll_check_timer); - /* No need to protect the streams list here, since the hrtimer is - * disabled before the stream is removed from list, and currently a - * single exclusive_stream is supported. - * XXX: revisit this when multiple concurrent streams are supported. - */ + mutex_lock(&dev_priv->perf.streams_lock); list_for_each_entry(stream, &dev_priv->perf.streams, link) { if (stream_have_data_unlocked(stream)) { dev_priv->perf.pollin[stream->engine] = true; wake_up(&dev_priv->perf.poll_wq[stream->engine]); } } + mutex_unlock(&dev_priv->perf.streams_lock); +} + +static enum hrtimer_restart poll_check_timer_cb(struct hrtimer *hrtimer) +{ + struct drm_i915_private *dev_priv = + container_of(hrtimer, typeof(*dev_priv), + perf.poll_check_timer); + + async_schedule(wake_up_perf_streams, dev_priv); hrtimer_forward_now(hrtimer, ns_to_ktime(POLL_PERIOD));