From patchwork Wed Apr 5 09:30:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 9664683 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8254B602B8 for ; Wed, 5 Apr 2017 16:30:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74A3E28354 for ; Wed, 5 Apr 2017 16:30:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6949228395; Wed, 5 Apr 2017 16:30:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1C28E28354 for ; Wed, 5 Apr 2017 16:30:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 231AA6E840; Wed, 5 Apr 2017 16:30:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id BFC256E83C for ; Wed, 5 Apr 2017 16:30:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491409829; x=1522945829; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=kn5uVA9wXIcUkeItNBK9ndSaWjcLcEGZ4TJxtR0O9Ew=; b=tKYzUMJ+3dIAfcO5eBepNRddeytgDha1mWEtOQe101TF2rp6KQKa3/Lu 4wXTm0R/q3u2FVpz2gF8GJM1vK+aTg==; Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Apr 2017 09:30:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,279,1486454400"; d="scan'208";a="69785733" Received: from omateolo-linux.fm.intel.com ([10.1.27.55]) by orsmga002.jf.intel.com with ESMTP; 05 Apr 2017 09:30:29 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Apr 2017 02:30:37 -0700 Message-Id: <1491384637-971-6-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491384637-971-1-git-send-email-oscar.mateo@intel.com> References: <1491384637-971-1-git-send-email-oscar.mateo@intel.com> Cc: Paulo Zanoni , Rodrigo Vivi Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Use the engine class to get the context size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Daniele Ceraolo Spurio Technically speaking, the context size is per engine class, not per instance. Cc: Tvrtko Ursulin Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Chris Wilson Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_lrc.c | 34 ++++++++++++++++++++++------------ drivers/gpu/drm/i915/intel_lrc.h | 7 ++++++- 2 files changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0dc1cc4..6b1fc4a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs, } /** - * intel_lr_context_size() - return the size of the context for an engine - * @engine: which engine to find the context size for + * intel_lr_class_context_size() - return the size of the context for a given + * engine class + * @dev_priv: i915 device private + * @class: which engine class to find the context size for * * Each engine may require a different amount of space for a context image, * so when allocating (or copying) an image, this function can be used to @@ -1921,25 +1923,33 @@ static void execlists_init_reg_state(u32 *regs, * in LRC mode, but does not include the "shared data page" used with * GuC submission. The caller should account for this if using the GuC. */ -uint32_t intel_lr_context_size(struct intel_engine_cs *engine) +uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, + enum intel_engine_class class) { int ret = 0; - WARN_ON(INTEL_GEN(engine->i915) < 8); + WARN_ON(INTEL_GEN(dev_priv) < 8); - switch (engine->id) { - case RCS: - if (INTEL_GEN(engine->i915) >= 9) + switch (class) { + case RENDER_CLASS: + switch (INTEL_GEN(dev_priv)) { + default: + DRM_ERROR("Unknown context size for GEN\n"); + case 9: ret = GEN9_LR_CONTEXT_RENDER_SIZE; - else + break; + case 8: ret = GEN8_LR_CONTEXT_RENDER_SIZE; + break; + } break; - case VCS: - case BCS: - case VECS: - case VCS2: + case VIDEO_DECODE_CLASS: + case VIDEO_ENHANCEMENT_CLASS: + case COPY_ENGINE_CLASS: ret = GEN8_LR_CONTEXT_OTHER_SIZE; break; + default: + MISSING_CASE(class); } return ret; diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index e8015e7..b3a4331 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -78,7 +78,12 @@ enum { struct drm_i915_private; struct i915_gem_context; -uint32_t intel_lr_context_size(struct intel_engine_cs *engine); +uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, + enum intel_engine_class class); +static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine) +{ + return intel_lr_class_context_size(engine->i915, engine->class); +} void intel_lr_context_resume(struct drm_i915_private *dev_priv); uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,