From patchwork Tue May 2 15:08:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 9708613 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7289B6021C for ; Tue, 2 May 2017 22:08:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64098284DA for ; Tue, 2 May 2017 22:08:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 58EB6284EE; Tue, 2 May 2017 22:08:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0D3CB284DA for ; Tue, 2 May 2017 22:08:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B76236E291; Tue, 2 May 2017 22:08:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1EBCE6E291 for ; Tue, 2 May 2017 22:08:24 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 May 2017 15:08:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.38,281,1491289200"; d="scan'208"; a="1142856690" Received: from omateolo-linux.fm.intel.com ([10.1.27.118]) by fmsmga001.fm.intel.com with ESMTP; 02 May 2017 15:08:23 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Tue, 2 May 2017 15:08:27 +0000 Message-Id: <1493737707-5478-1-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [RFC] tests/pm_sseu: Add subtest to verify UMD can configure render powerclock state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Dmitry Rogozhkin Cc: Chris Wilson Signed-off-by: Oscar Mateo --- tests/pm_sseu.c | 105 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/tests/pm_sseu.c b/tests/pm_sseu.c index 7d4b33c..1fb36c5 100644 --- a/tests/pm_sseu.c +++ b/tests/pm_sseu.c @@ -352,6 +352,108 @@ full_enable(void) check_full_enable(&stat); } +#define GEN8_R_PWR_CLK_STATE (0x20C8) +#define GEN8_RPCS_ENABLE (1 << 31) + +#define MI_STORE_REGISTER_MEM_64_BIT_ADDR ((0x24 << 23) | 2) + +static uint32_t read_pwrclk_state(drm_intel_bufmgr *bufmgr, + struct intel_batchbuffer *batch, + drm_intel_context *context) +{ + uint32_t rpcs_config; + uint32_t *data; + drm_intel_bo *dst_bo; + + dst_bo = drm_intel_bo_alloc(bufmgr, "dst", 4, 4096); + + BEGIN_BATCH(3, 1); + OUT_BATCH(MI_STORE_REGISTER_MEM_64_BIT_ADDR); + OUT_BATCH(GEN8_R_PWR_CLK_STATE); + OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); + ADVANCE_BATCH(); + + intel_batchbuffer_flush_with_context(batch, context); + + drm_intel_bo_map(dst_bo, 1); + + data = dst_bo->virtual; + rpcs_config = *data; + + drm_intel_bo_unmap(dst_bo); + + drm_intel_bo_unreference(dst_bo); + + return rpcs_config; +} + +#define LOCAL_MI_LOAD_REGISTER_IMM (0x22 << 23) + +#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) +#define PIPE_CONTROL_CS_STALL (1<<20) +#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) +#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) +#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) +#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) + +static void write_pwrclk_state(drm_intel_bufmgr *bufmgr, + struct intel_batchbuffer *batch, + drm_intel_context *context, + uint32_t rpcs_config) +{ + drm_intel_bo *dst_bo; + + dst_bo = drm_intel_bo_alloc(bufmgr, "scratch", 4, 4096); + + BEGIN_BATCH(9, 1); + OUT_BATCH(LOCAL_MI_LOAD_REGISTER_IMM | 1); + OUT_BATCH(GEN8_R_PWR_CLK_STATE); + OUT_BATCH(rpcs_config); + OUT_BATCH(GFX_OP_PIPE_CONTROL(6)); + OUT_BATCH(PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | + PIPE_CONTROL_DEPTH_CACHE_FLUSH | + PIPE_CONTROL_DC_FLUSH_ENABLE | + PIPE_CONTROL_FLUSH_ENABLE | + PIPE_CONTROL_CS_STALL); + OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + intel_batchbuffer_flush_with_context(batch, context); + + drm_intel_bo_unreference(dst_bo); +} + +/* Makes sure userspace can configure GEN8_R_PWR_CLK_STATE (e.g. is whitelisted) */ +static void +pwrclk_state(void) +{ + drm_intel_context *context; + uint32_t rpcs_config; + bool rpcs_enabled; + + /* + * Gen8 BDW is the first case in which usermode can configure their + * own render power gating + */ + igt_require(gem.gen >= 8); + + context = drm_intel_gem_context_create(gem.bufmgr); + + rpcs_config = read_pwrclk_state(gem.bufmgr, gem.batch, context); + rpcs_enabled = rpcs_config & GEN8_RPCS_ENABLE; + + rpcs_config ^= GEN8_RPCS_ENABLE; + write_pwrclk_state(gem.bufmgr, gem.batch, context, rpcs_config); + + rpcs_config = read_pwrclk_state(gem.bufmgr, gem.batch, context); + igt_assert_neq(rpcs_enabled, !!(rpcs_config & GEN8_RPCS_ENABLE)); + + drm_intel_gem_context_destroy(context); +} + static void exit_handler(int sig) { @@ -370,4 +472,7 @@ igt_main igt_subtest("full-enable") full_enable(); + + igt_subtest("pwrclk-state") + pwrclk_state(); }