From patchwork Mon May 22 18:07:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bloomfield, Jon" X-Patchwork-Id: 9741263 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 643366034C for ; Mon, 22 May 2017 18:07:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 50C27205A4 for ; Mon, 22 May 2017 18:07:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 33C752873A; Mon, 22 May 2017 18:07:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C742F205A4 for ; Mon, 22 May 2017 18:07:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B96489E0C; Mon, 22 May 2017 18:07:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9FB7989E0C for ; Mon, 22 May 2017 18:07:53 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP; 22 May 2017 11:07:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,378,1491289200"; d="scan'208";a="265014552" Received: from relo-linux-7.fm.intel.com ([10.1.27.120]) by fmsmga004.fm.intel.com with ESMTP; 22 May 2017 11:07:50 -0700 From: Jon Bloomfield To: intel-gfx@lists.freedesktop.org Date: Mon, 22 May 2017 11:07:25 -0700 Message-Id: <1495476445-23324-1-git-send-email-jon.bloomfield@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH] drm/i915: Serialize GTT Updates on BXT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP BXT requires accesses to the GTT (i.e. PTE updates) to be serialized when IOMMU is enabled. This patch guarantees this by wrapping all updates in stop_machine and using a flushing read to guarantee that the GTT writes have reached their destination before restarting. Signed-off-by: Jon Bloomfield Signed-off-by: John Harrison --- drivers/gpu/drm/i915/i915_gem_gtt.c | 106 ++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 7c769d7..6360d92 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2191,6 +2191,100 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm, gen8_set_pte(>t_base[i], scratch_pte); } +#ifdef CONFIG_INTEL_IOMMU +struct insert_page { + struct i915_address_space *vm; + dma_addr_t addr; + u64 offset; + enum i915_cache_level level; +}; + +static int gen8_ggtt_insert_page__cb(void *_arg) +{ + struct insert_page *arg = _arg; + + struct drm_i915_private *dev_priv = arg->vm->i915; + + gen8_ggtt_insert_page(arg->vm, arg->addr, + arg->offset, arg->level, 0); + + POSTING_READ(GFX_FLSH_CNTL_GEN6); + + return 0; +} + +static void gen8_ggtt_insert_page__BKL(struct i915_address_space *vm, + dma_addr_t addr, + u64 offset, + enum i915_cache_level level, + u32 unused) +{ + struct insert_page arg = { vm, addr, offset, level }; + + stop_machine(gen8_ggtt_insert_page__cb, &arg, NULL); +} + + +struct insert_entries { + struct i915_address_space *vm; + struct sg_table *st; + u64 start; + enum i915_cache_level level; +}; + +static int gen8_ggtt_insert_entries__cb(void *_arg) +{ + struct insert_entries *arg = _arg; + + struct drm_i915_private *dev_priv = arg->vm->i915; + + gen8_ggtt_insert_entries(arg->vm, arg->st, + arg->start, arg->level, 0); + + POSTING_READ(GFX_FLSH_CNTL_GEN6); + + return 0; +} + +static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, + struct sg_table *st, + u64 start, + enum i915_cache_level level, + u32 unused) +{ + struct insert_entries arg = { vm, st, start, level }; + + stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); +} + +struct clear_range { + struct i915_address_space *vm; + u64 start; + u64 length; +}; + +static int gen8_ggtt_clear_range__cb(void *_arg) +{ + struct clear_range *arg = _arg; + + struct drm_i915_private *dev_priv = arg->vm->i915; + + gen8_ggtt_clear_range(arg->vm, arg->start, arg->length); + + POSTING_READ(GFX_FLSH_CNTL_GEN6); + + return 0; +} + +static void gen8_ggtt_clear_range__BKL(struct i915_address_space *vm, + u64 start, + u64 length) +{ + struct clear_range arg = { vm, start, length }; + stop_machine(gen8_ggtt_clear_range__cb, &arg, NULL); +} +#endif + static void gen6_ggtt_clear_range(struct i915_address_space *vm, u64 start, u64 length) { @@ -2789,6 +2883,18 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) ggtt->base.insert_entries = gen8_ggtt_insert_entries; +#ifdef CONFIG_INTEL_IOMMU + /* Serialize GTT updates on BXT if VT-d is on. */ + if (IS_BROXTON(dev_priv) && intel_iommu_gfx_mapped) { + ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; + ggtt->base.insert_page = gen8_ggtt_insert_page__BKL; + if (!USES_FULL_PPGTT(dev_priv) || + intel_scanout_needs_vtd_wa(dev_priv)) { + ggtt->base.clear_range = gen8_ggtt_clear_range__BKL; + } + } +#endif + ggtt->invalidate = gen6_ggtt_invalidate; return ggtt_probe_common(ggtt, size);