From patchwork Wed Jun 7 10:41:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srinivas, Vidya" X-Patchwork-Id: 9771275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 38FCA6034B for ; Wed, 7 Jun 2017 10:34:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 101831FF4A for ; Wed, 7 Jun 2017 10:34:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 04C1E20453; Wed, 7 Jun 2017 10:34:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BD8021FF4A for ; Wed, 7 Jun 2017 10:34:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F1F536E254; Wed, 7 Jun 2017 10:34:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 699C56E251 for ; Wed, 7 Jun 2017 10:34:49 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Jun 2017 03:34:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,310,1493708400"; d="scan'208";a="110202025" Received: from vsrini4-ubuntu-intel.iind.intel.com ([10.223.25.59]) by orsmga005.jf.intel.com with ESMTP; 07 Jun 2017 03:34:47 -0700 From: Vidya Srinivas To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Jun 2017 16:11:48 +0530 Message-Id: <1496832108-32594-9-git-send-email-vidya.srinivas@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496832108-32594-1-git-send-email-vidya.srinivas@intel.com> References: <1496811086-28706-1-git-send-email-vidya.srinivas@intel.com> <1496832108-32594-1-git-send-email-vidya.srinivas@intel.com> Cc: Vidya Srinivas Subject: [Intel-gfx] [PATCH 8/8] drm/i915: Add NV12 support to intel_framebuffer_init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) Link: https://patchwork.kernel.org/patch/6426221/ Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 300f589..6e89421 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14767,6 +14767,21 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, goto err; } break; + case DRM_FORMAT_NV12: + if (!mode_cmd->offsets[1]) + DRM_ERROR("uv start offset not set\n"); + if (mode_cmd->pitches[0] != mode_cmd->pitches[1] || + mode_cmd->handles[0] != mode_cmd->handles[1]) + DRM_ERROR("y & uv subplanes have different params\n"); + if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED && + (mode_cmd->offsets[1] & 0xFFF)) + DRM_ERROR("tile-Yf uv offset 0x%x isn't starting on new tile-row\n", + mode_cmd->offsets[1]); + if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED && + ((mode_cmd->offsets[1] / mode_cmd->pitches[1]) % 4)) + DRM_ERROR("tile-Y uv offset 0x%x isn't 4-line aligned\n", + mode_cmd->offsets[1]); + break; default: DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name));