| Message ID | 1497939034-5234-4-git-send-email-vidya.srinivas@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> -Clint On 06/19/2017 11:10 PM, Vidya Srinivas wrote: > From: Chandra Konduru <chandra.konduru@intel.com> > > This patch sets appropriate scaler mode for NV12 format. > In this mode, skylake scaler does either chroma-upsampling or > chroma-upsampling and resolution scaling > > v2: Review comments from Ville addressed > NV12 case to be checked first for setting > the scaler > > v3: Rebased (me) > > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_atomic.c | 8 +++++++- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 41ddd25..5c3b120 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6390,6 +6390,7 @@ enum { > #define PS_SCALER_MODE_MASK (3 << 28) > #define PS_SCALER_MODE_DYN (0 << 28) > #define PS_SCALER_MODE_HQ (1 << 28) > +#define PS_SCALER_MODE_NV12 (2 << 28) > #define PS_PLANE_SEL_MASK (7 << 25) > #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) > #define PS_FILTER_MASK (3 << 23) > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c > index 36d4e63..808f8e6 100644 > --- a/drivers/gpu/drm/i915/intel_atomic.c > +++ b/drivers/gpu/drm/i915/intel_atomic.c > @@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, > } > > /* set scaler mode */ > - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { > + if (plane_state && plane_state->base.fb && > + plane_state->base.fb->format->format == > + DRM_FORMAT_NV12) { > + DRM_ERROR("NV12 format setting scaler mode\n"); > + scaler_state->scalers[*scaler_id].mode = > + PS_SCALER_MODE_NV12; > + } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { > scaler_state->scalers[*scaler_id].mode = 0; > } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { > /*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 41ddd25..5c3b120 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6390,6 +6390,7 @@ enum { #define PS_SCALER_MODE_MASK (3 << 28) #define PS_SCALER_MODE_DYN (0 << 28) #define PS_SCALER_MODE_HQ (1 << 28) +#define PS_SCALER_MODE_NV12 (2 << 28) #define PS_PLANE_SEL_MASK (7 << 25) #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) #define PS_FILTER_MASK (3 << 23) diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 36d4e63..808f8e6 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, } /* set scaler mode */ - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { + if (plane_state && plane_state->base.fb && + plane_state->base.fb->format->format == + DRM_FORMAT_NV12) { + DRM_ERROR("NV12 format setting scaler mode\n"); + scaler_state->scalers[*scaler_id].mode = + PS_SCALER_MODE_NV12; + } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { scaler_state->scalers[*scaler_id].mode = 0; } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { /*