From patchwork Tue Aug 15 21:31:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9901891 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 04A69603B5 for ; Tue, 15 Aug 2017 13:32:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC1DD287EC for ; Tue, 15 Aug 2017 13:32:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E0D80287F2; Tue, 15 Aug 2017 13:32:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 568C0287F0 for ; Tue, 15 Aug 2017 13:32:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9EDB86E2AF; Tue, 15 Aug 2017 13:32:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D96AA89D1D; Tue, 15 Aug 2017 13:32:26 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2017 06:32:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,377,1498546800"; d="scan'208";a="300352097" Received: from zhiwang1-mobl.bj.intel.com ([10.238.154.56]) by fmsmga004.fm.intel.com with ESMTP; 15 Aug 2017 06:32:25 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org Date: Wed, 16 Aug 2017 05:31:09 +0800 Message-Id: <1502832675-6123-2-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502832675-6123-1-git-send-email-zhi.a.wang@intel.com> References: <1502832675-6123-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [RFC 1/7] drm/i915: Introduce a bitmap to indicate available PPAT entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To introduce the dynamic private PAT management in GVT-g, the host i915 is required to tell GVT-g the unused PAT entries. The available PPAT entries are showed in a bitmap. For platforms which don't have private PAT, the bitmap is set to "empty", so GVT-g will not enable private PAT management function. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_gem_gtt.c | 13 ++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 768a92b..79fc680 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2302,6 +2302,9 @@ struct drm_i915_private { DECLARE_HASHTABLE(mm_structs, 7); struct mutex mm_lock; +#define MAX_PPAT_INDEX 8 + DECLARE_BITMAP(avail_ppat_bitmap, MAX_PPAT_INDEX); + /* Kernel Modesetting */ struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 090ceb7..b9665b7 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2758,7 +2758,7 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); - if (!USES_PPGTT(dev_priv)) + if (!USES_PPGTT(dev_priv)) { /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, * so RTL will always use the value corresponding to * pat_sel = 000". @@ -2774,6 +2774,17 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) */ pat = GEN8_PPAT(0, GEN8_PPAT_UC); + set_bit(1, dev_priv->avail_ppat_bitmap); + set_bit(2, dev_priv->avail_ppat_bitmap); + set_bit(3, dev_priv->avail_ppat_bitmap); + } + + /* PPAT entries 4 - 7 are unused, mark them available */ + set_bit(4, dev_priv->avail_ppat_bitmap); + set_bit(5, dev_priv->avail_ppat_bitmap); + set_bit(6, dev_priv->avail_ppat_bitmap); + set_bit(7, dev_priv->avail_ppat_bitmap); + /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b * write would work. */ I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);