From patchwork Tue Aug 15 21:31:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9901901 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F3CAE60244 for ; Tue, 15 Aug 2017 13:32:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E6EC9287EC for ; Tue, 15 Aug 2017 13:32:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DBF3A287F2; Tue, 15 Aug 2017 13:32:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8D394287EC for ; Tue, 15 Aug 2017 13:32:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4E006E2C7; Tue, 15 Aug 2017 13:32:36 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D1FEB6E2BC; Tue, 15 Aug 2017 13:32:34 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2017 06:32:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,377,1498546800"; d="scan'208";a="300352150" Received: from zhiwang1-mobl.bj.intel.com ([10.238.154.56]) by fmsmga004.fm.intel.com with ESMTP; 15 Aug 2017 06:32:33 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org Date: Wed, 16 Aug 2017 05:31:14 +0800 Message-Id: <1502832675-6123-7-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502832675-6123-1-git-send-email-zhi.a.wang@intel.com> References: <1502832675-6123-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [RFC 6/7] drm/i915/gvt: Introduce virtual private PAT support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Introduce PPAT MMIO handlers. The mapping between virtual PPAT indexes and physical PPAT indexes needs to be re-built after a guest write its virtual PPAT configuration. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/gvt/gtt.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/gvt/gtt.h | 4 +++- drivers/gpu/drm/i915/gvt/handlers.c | 16 ++++++++++++++-- 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 1d7077d..6ec2a03 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -2374,6 +2374,32 @@ static void put_private_pat_index(struct intel_gvt *gvt, unsigned int index) set_bit(index, gtt->avail_ppat_bitmap); } +int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu) +{ + struct intel_gvt *gvt = vgpu->gvt; + struct intel_gvt_gtt_pat_ops *ops = gvt->gtt.pat_ops; + struct intel_vgpu_gtt *gtt = &vgpu->gtt; + unsigned int value; + void *mem = &vgpu_vreg(vgpu, GEN8_PRIVATE_PAT_LO); + int i; + + if (gtt->ppat_configured) { + /* Release all indexes first */ + for (i = 0; i < gvt->gtt.max_ppat_index; i++) + put_private_pat_index(gvt, gtt->ppat_index[i]); + } + + for (i = 0; i < gvt->gtt.max_ppat_index; i++) { + value = ops->get_pat_value(mem, i, NULL); + gtt->ppat_index[i] = get_private_pat_index(gvt, value); + } + + retire_vgpu_ppgtt_mm(vgpu); + + gtt->ppat_configured = true; + return 0; +} + /** * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object * @vgpu: a vGPU diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index a83d1f0..ab3e771 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h @@ -223,7 +223,8 @@ struct intel_vgpu_gtt { struct list_head oos_page_list_head; struct list_head post_shadow_list_head; struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX]; - + bool ppat_configured; + unsigned int ppat_index[MAX_PPAT_INDEX]; }; extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); @@ -234,6 +235,7 @@ extern int intel_gvt_init_gtt(struct intel_gvt *gvt); void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); extern void intel_gvt_clean_gtt(struct intel_gvt *gvt); +extern int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu); extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, int page_table_level, void *root_entry); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 825abfc..e07264f 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1369,6 +1369,18 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); } +static int gen8_ppat_write(struct intel_vgpu *vgpu, unsigned int offset, + void *p_data, unsigned int bytes) +{ + int ret; + + ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); + if (ret) + return ret; + + return intel_vgpu_update_virtual_ppat(vgpu); +} + static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { @@ -2543,8 +2555,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS, NULL, gen8_ppat_write); + MMIO_DH(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS, NULL, gen8_ppat_write); MMIO_D(GAMTARBMODE, D_BDW_PLUS);