From patchwork Fri Aug 18 18:34:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jason Ekstrand X-Patchwork-Id: 9909729 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 17A37600CC for ; Fri, 18 Aug 2017 18:34:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0BC8928D1F for ; Fri, 18 Aug 2017 18:34:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0028328D3E; Fri, 18 Aug 2017 18:34:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A498428D1F for ; Fri, 18 Aug 2017 18:34:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DD736E052; Fri, 18 Aug 2017 18:34:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id DBBE96E052 for ; Fri, 18 Aug 2017 18:34:43 +0000 (UTC) Received: by mail-pg0-x243.google.com with SMTP id 83so16216152pgb.4 for ; Fri, 18 Aug 2017 11:34:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jlekstrand-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=v0P9ClyNM8a40hKmN4FOqsO3P1Bd9oBAF0I4uiWvy10=; b=aZckfrBVKKd1HeRdnlHQmmEMHUIKiNdNU7i3VO/O0L1mvB6EOiavU9jt+Aj9TpVVRI EX1EjTwmDYXXSEjXLCBZEfajyOZ++z7ZTbU55i2zCosRLN1OT20oYqfGEkJkUK+G108p /PyllIoS/EQ807MTvmfGudAkNxCbAFinmewO1b7tZIEhA+y9FjBq+2qsHHHPWOF5ikC1 1HRb16iZa+PEAxXGzpIUiea1wJxF1EciciRxaA/X28qYKmtyoCNSIxHOxe8VSYRYkbPc zOSjD0Q7xrXHabNEErnPXfF4UznsQw1GUzpE0QzVTaIEIVg+FUGfVzsM8f5Fd99Aacmc DrjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=v0P9ClyNM8a40hKmN4FOqsO3P1Bd9oBAF0I4uiWvy10=; b=euGbmcE6RI2cNBENUm8pAYEIaRWu9pM0I6KblHwdx/HHel3eYv4HQ73CsRcXDp4lEr sV0tzVChYa0wlSkaXYXx0/7mOubkAjl2Torf2R3MehSA0AIeSuLVK6sbNjMAakr0CW/f pWN+GN2bAEfFkVIs3Mq7mmqqg11PwN9kCQFlHY174LhbonuqfW8d5DovsBW6sfib9ksT AjqPj+JY15HMgXg3TPMUvqNaSObvczqAwdMnjKf8TxR2R3WWDSuggxHjcprkqgYXYR9u uQdEVUOXJYQGME7diCRXEGsvKkkezEsHwUqI5oAI+hEHJJ5FtjyAytHQEnq9ulUI1KyN S+LQ== X-Gm-Message-State: AHYfb5g3n99VCl9aVEHI07wmn4Qtxp0dJqdCchHNeIYCo8k8k5HNzAaw Ukm+YMGNz44PfXczjySsBA== X-Received: by 10.99.126.91 with SMTP id o27mr9204278pgn.202.1503081283151; Fri, 18 Aug 2017 11:34:43 -0700 (PDT) Received: from omlet.ak.intel.com ([134.134.139.78]) by smtp.gmail.com with ESMTPSA id m2sm10514364pgs.72.2017.08.18.11.34.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 Aug 2017 11:34:42 -0700 (PDT) From: Jason Ekstrand X-Google-Original-From: Jason Ekstrand To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Fri, 18 Aug 2017 11:34:40 -0700 Message-Id: <1503081280-1813-1-git-send-email-jason.ekstrand@intel.com> X-Mailer: git-send-email 2.5.0.400.gff86faf MIME-Version: 1.0 Cc: Jason Ekstrand , Ben Widawsky Subject: [Intel-gfx] [PATCH] i915, drm/fourcc: Improve the CCS modifier documentation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This updates the documentation on the intel CCS modifiers for a couple of reasons: 1) The old documentation required that the CCS modifier only be used with 8888 formats. While i915 currently only supports CCS scanout with 8888 formats (and advertises such through the blob format), CCS can be used with many other formats. Mesa, in particular, can handle CCS on the full range of formats supported by the hardware. For image sharing entirely within userspace, we don't want this restriction. 2) The old documentation specified the scaling factor in terms of pixels which breaks down when you start using formats which are not 32-bit. By specifying it in terms of cache lines and tiles, we can properly specify the scale-down relationship with no format size assumptions. 3) The new comment provides more detail about the "real" layout of CCS on Sky Lake and also points out that the reason why Y tiling is important is because it affects row pitch calculations. 4) We shouldn't be documenting the Yf CCS modifier yet. Userspace is incapable of generating it right now and we don't fully know how it works yet. Trying to fully describe it is premature. Signed-off-by: Jason Ekstrand Cc: Ben Widawsky Cc: Ville Syrjälä --- include/uapi/drm/drm_fourcc.h | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3ad838d..9670da4 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -266,21 +266,30 @@ extern "C" { /* * Intel color control surface (CCS) for render compression * - * The framebuffer format must be one of the 8:8:8:8 RGB formats. - * The main surface will be plane index 0 and must be Y/Yf-tiled, - * the CCS will be plane index 1. - * - * Each CCS tile matches a 1024x512 pixel area of the main surface. - * To match certain aspects of the 3D hardware the CCS is - * considered to be made up of normal 128Bx32 Y tiles, Thus - * the CCS pitch must be specified in multiples of 128 bytes. - * - * In reality the CCS tile appears to be a 64Bx64 Y tile, composed - * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. - * But that fact is not relevant unless the memory is accessed - * directly. + * The image format must be compatible with CCS_E (lossless render + * compression) as specified in the PRM for the relevant hardware. + * The main surface will be plane index 0 and must be Y-tiled, + * the CCS will be plane index 1 and is also Y-tiled. + * + * Each 64B cache line in the CCS (a region of 16B x 4 rows when + * Y-tiled) corresponds to a region of 32x16 cache lines in the main + * surface. (As a corollary, each CCS tile corresponds to an area of + * 32x16 tiles in the main surface.) This relationship holds regardless + * of the size of the number of bits per pixel of the image format. + * + * In reality, the cache lines in the CCS tile are proportioned in an + * 8B x 8 row configuration with each byte being 2x2 2-bit CCS entries. + * However, CCS is documented as Y-tiled with the scaling relationship + * described in terms of cache lines as above so we consider it to be + * Y-tiled for the purpose of specifying this modifier. This means that + * the row pitch for the CCS assumes 128B/tile. */ #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) + +/* Reserved for the Yf version of the TILED_CCS modifier. + * + * Exact definition TBD. + */ #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) /*