From patchwork Fri Sep 1 07:25:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9933647 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 09F7F6016C for ; Fri, 1 Sep 2017 07:22:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F01DF2855D for ; Fri, 1 Sep 2017 07:22:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E52DD2857D; Fri, 1 Sep 2017 07:22:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 306B62855D for ; Fri, 1 Sep 2017 07:22:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D9D7F6E7F1; Fri, 1 Sep 2017 07:22:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 23FB66E7FA for ; Fri, 1 Sep 2017 07:22:24 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP; 01 Sep 2017 00:22:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,457,1498546800"; d="scan'208";a="144393444" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2017 00:22:22 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Fri, 1 Sep 2017 12:55:17 +0530 Message-Id: <1504250723-32018-15-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1504250723-32018-1-git-send-email-sagar.a.kamble@intel.com> References: <1504250723-32018-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH 14/20] drm/i915/slpc: Add debugfs support to read/write/revert the parameters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds two debugfs interfaces: 1. i915_slpc_paramlist: List of all parameters that Host can configure. Currently listing id and description of each. 2. i915_slpc_param_ctl: This allows to change the parameters. Syntax is: echo "write " > i915_slpc_param_ctl. echo "read " > i915_slpc_param_ctl; cat i915_slpc_param_ctl revert allows to set to default SLPC internal values. Syntax is: echo "revert " > i915_slpc_param_ctl. Added support to set/read parameters and unset the parameters which will revert them to default SLPC internal values. Also added RPM ref. cover around set/unset calls. Explicit SLPC reset is needed on setting/unsetting some of the parameters. Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_debugfs.c | 19 +++++ drivers/gpu/drm/i915/intel_slpc.c | 158 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_slpc.h | 6 ++ 3 files changed, 183 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2606554..91edc2f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2359,6 +2359,23 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data) return 0; } +static int i915_slpc_paramlist_info(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + int i; + + if (!dev_priv->guc.slpc.active) { + seq_puts(m, "SLPC not active\n"); + return 0; + } + + seq_puts(m, "Param id\tParam description\n"); + for (i = 0; i < SLPC_MAX_PARAM; i++) + seq_printf(m, "%8d\t%s\n", slpc_paramlist[i].id, + slpc_paramlist[i].description); + return 0; +} + static int i915_guc_load_status_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -4833,6 +4850,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1}, {"i915_guc_stage_pool", i915_guc_stage_pool, 0}, {"i915_huc_load_status", i915_huc_load_status_info, 0}, + {"i915_slpc_paramlist", i915_slpc_paramlist_info, 0}, {"i915_frequency_info", i915_frequency_info, 0}, {"i915_hangcheck_info", i915_hangcheck_info, 0}, {"i915_reset_info", i915_reset_info, 0}, @@ -4896,6 +4914,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) {"i915_dp_test_type", &i915_displayport_test_type_fops}, {"i915_dp_test_active", &i915_displayport_test_active_fops}, {"i915_guc_log_control", &i915_guc_log_control_fops}, + {"i915_slpc_param_ctl", &i915_slpc_param_ctl_fops}, {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops} }; diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c index 43767c9..7410e2d 100644 --- a/drivers/gpu/drm/i915/intel_slpc.c +++ b/drivers/gpu/drm/i915/intel_slpc.c @@ -25,6 +25,8 @@ #include #include "i915_drv.h" #include "intel_uc.h" +#include +#include struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = { {SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"}, @@ -641,3 +643,159 @@ void intel_slpc_disable(struct intel_slpc *slpc) slpc->active = false; } + +static int slpc_param_ctl_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + struct intel_slpc *slpc = &dev_priv->guc.slpc; + + if (!slpc->active) { + seq_puts(m, "SLPC not active\n"); + return 0; + } + + seq_printf(m, "%s=%u, override=%s\n", + slpc_paramlist[slpc->debug_param_id].description, + slpc->debug_param_value, + yesno(!!slpc->debug_param_override)); + + return 0; +} + +static int slpc_param_ctl_open(struct inode *inode, struct file *file) +{ + return single_open(file, slpc_param_ctl_show, inode->i_private); +} + +static const char *read_token = "read", *write_token = "write", + *revert_token = "revert"; + +/* + * Parse SLPC parameter control strings: (Similar to Pipe CRC handling) + * command: wsp* op wsp+ param id wsp+ [value] wsp* + * op: "read"/"write"/"revert" + * param id: slpc_param_id + * value: u32 value + * wsp: (#0x20 | #0x9 | #0xA)+ + * + * eg.: + * "read 0" -> read SLPC_PARAM_TASK_ENABLE_GTPERF + * "write 7 500" -> set SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to 500MHz + * "revert 7" -> revert SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to + * default value. + */ +static int slpc_param_ctl_parse(char *buf, size_t len, char **op, + u32 *id, u32 *value) +{ +#define MAX_WORDS 3 + int n_words; + char *words[MAX_WORDS]; + ssize_t ret; + + n_words = buffer_tokenize(buf, words, MAX_WORDS); + if (!(n_words == 3) && !(n_words == 2)) { + DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", + MAX_WORDS); + return -EINVAL; + } + + if (strcmp(words[0], read_token) && strcmp(words[0], write_token) && + strcmp(words[0], revert_token)) { + DRM_DEBUG_DRIVER("unknown operation\n"); + return -EINVAL; + } + + *op = words[0]; + + ret = kstrtou32(words[1], 0, id); + if (ret) + return ret; + + if (n_words == 3) { + ret = kstrtou32(words[2], 0, value); + if (ret) + return ret; + } + + return 0; +} + +static ssize_t slpc_param_ctl_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + struct intel_slpc *slpc = &dev_priv->guc.slpc; + char *tmpbuf, *op = NULL; + u32 id, value; + int ret; + + if (len == 0) + return 0; + + if (len > 40) { + DRM_DEBUG_DRIVER("expected <40 chars into slpc_param_ctl\n"); + return -E2BIG; + } + + tmpbuf = kmalloc(len + 1, GFP_KERNEL); + if (!tmpbuf) + return -ENOMEM; + + if (copy_from_user(tmpbuf, ubuf, len)) { + ret = -EFAULT; + goto out; + } + tmpbuf[len] = '\0'; + + ret = slpc_param_ctl_parse(tmpbuf, len, &op, &id, &value); + + if (id >= SLPC_MAX_PARAM) { + ret = -EINVAL; + goto out; + } + + if (!strcmp(op, read_token)) { + intel_slpc_get_param(slpc, id, + &slpc->debug_param_override, + &slpc->debug_param_value); + slpc->debug_param_id = id; + } else if (!strcmp(op, write_token) || !strcmp(op, revert_token)) { + if ((id >= SLPC_PARAM_TASK_ENABLE_GTPERF) && + (id <= SLPC_PARAM_TASK_DISABLE_DCC)) { + DRM_DEBUG_DRIVER("Tasks are not controlled by " + "this interface\n"); + ret = -EINVAL; + goto out; + } + + /* + * After updating parameters, RESET event has to be sent to GuC + * SLPC for ensuring parameters take effect. + */ + intel_runtime_pm_get(dev_priv); + if (!strcmp(op, write_token)) + intel_slpc_set_param(slpc, id, value); + else if (!strcmp(op, revert_token)) + intel_slpc_unset_param(slpc, id); + intel_slpc_enable(slpc); + intel_runtime_pm_put(dev_priv); + } + +out: + kfree(tmpbuf); + if (ret < 0) + return ret; + + *offp += len; + return len; +} + +const struct file_operations i915_slpc_param_ctl_fops = { + .owner = THIS_MODULE, + .open = slpc_param_ctl_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = slpc_param_ctl_write +}; diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h index a5132d4..d2d7448 100644 --- a/drivers/gpu/drm/i915/intel_slpc.h +++ b/drivers/gpu/drm/i915/intel_slpc.h @@ -32,6 +32,10 @@ struct intel_slpc { /* i915 cached SLPC frequency limits */ u32 min_unslice_freq; u32 max_unslice_freq; + + u32 debug_param_id; + u32 debug_param_value; + u32 debug_param_override; }; enum slpc_status { @@ -241,6 +245,8 @@ struct slpc_param { #define SLPC_PARAM_TASK_DISABLED 2 #define SLPC_PARAM_TASK_UNKNOWN 3 +extern const struct file_operations i915_slpc_param_ctl_fops; + /* intel_slpc.c */ void intel_slpc_set_param(struct intel_slpc *slpc, u32 id, u32 value); void intel_slpc_unset_param(struct intel_slpc *slpc, u32 id);