From patchwork Thu Sep 7 10:07:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9942035 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7DF79602CC for ; Thu, 7 Sep 2017 10:04:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91E1128618 for ; Thu, 7 Sep 2017 10:04:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 86E7F2861C; Thu, 7 Sep 2017 10:04:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DBCC028618 for ; Thu, 7 Sep 2017 10:04:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C8656E8E1; Thu, 7 Sep 2017 10:04:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97BA46E8E0 for ; Thu, 7 Sep 2017 10:04:43 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2017 03:04:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,357,1500966000"; d="scan'208";a="146506744" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by orsmga005.jf.intel.com with ESMTP; 07 Sep 2017 03:04:42 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Thu, 7 Sep 2017 15:37:56 +0530 Message-Id: <1504778877-18822-8-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1504778877-18822-1-git-send-email-sagar.a.kamble@intel.com> References: <1504778877-18822-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH i-g-t 7/8] tests/perf: Add testcase to verify mmio X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Sagar Arun Kamble --- tests/intel_perf_dapc.c | 291 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 291 insertions(+) diff --git a/tests/intel_perf_dapc.c b/tests/intel_perf_dapc.c index 1831a81..ac6f3d1 100644 --- a/tests/intel_perf_dapc.c +++ b/tests/intel_perf_dapc.c @@ -1138,6 +1138,291 @@ test_perf_ts(void) igt_waitchildren(); } +static char * +read_debugfs_record(int device, const char *file, const char *key) +{ + FILE *fp; + int fd; + char *line = NULL; + size_t line_buf_size = 0; + int len = 0; + int key_len = strlen(key); + char *value = NULL; + + fd = igt_debugfs_open(device, file, O_RDONLY); + fp = fdopen(fd, "r"); + igt_require(fp); + + while ((len = getline(&line, &line_buf_size, fp)) > 0) { + + if (line[len - 1] == '\n') + line[len - 1] = '\0'; + + if (strncmp(key, line, key_len) == 0 && + line[key_len] == ':' && + line[key_len + 1] == ' ') { + value = strdup(line + key_len + 2); + goto done; + } + } + + igt_assert(!"reached"); +done: + free(line); + fclose(fp); + close(fd); + return value; +} + +static uint64_t +read_debugfs_u64_record(int fd, const char *file, const char *key) +{ + char *str_val = read_debugfs_record(fd, file, key); + uint64_t val; + + igt_require(str_val); + + val = strtoull(str_val, NULL, 0); + free(str_val); + + return val; +} + +/* Logic taken from i915 source. */ +static uint64_t +intel_rc6_residency_us(uint64_t time_hw) +{ + uint64_t units, div; + + if (IS_GEMINILAKE(devid) || IS_BROXTON(devid)) { + units = 1000; + div = 1200; /* 833.33ns */ + } else { + units = 128000; /* 1.28us */ + div = 100000; + } + + return ((time_hw * units) / div); +} + +struct oa_mmio_sample { + uint32_t mmio[2]; + uint8_t oa_report[]; +}; + +static void +verify_oa_mmio(uint8_t *perf_reports, int num_reports, size_t report_size, + uint64_t *pre_mmio_residency, uint64_t *post_mmio_residency) +{ + struct oa_mmio_sample *sample; + uint64_t rc6_residency; + uint64_t rc6p_residency; + uint32_t *oa_report; + + igt_debug("pre rc6 residency = %lu, rc6p residency = %lu, " + "post rc6 residency = %lu, rc6p residency = %lu\n", + pre_mmio_residency[0], pre_mmio_residency[1], + post_mmio_residency[0], post_mmio_residency[1]); + + for (int i = 0; i < num_reports; i++) { + size_t offset = i * report_size; + + sample = (struct oa_mmio_sample *) (perf_reports + offset); + oa_report = (uint32_t *) sample->oa_report; + + rc6_residency = intel_rc6_residency_us(sample->mmio[0]); + rc6p_residency = intel_rc6_residency_us(sample->mmio[1]); + + igt_debug("read mmio: rc6 = %u, rc6 residency = %lu, " + "rc6p = %u, rc6p residency = %lu\n", + sample->mmio[0], rc6_residency, + sample->mmio[1], rc6p_residency); + + igt_debug("read report: reason = %x, timestamp = %x\n", + oa_report[0], oa_report[1]); + + if (!oa_report[0]) { + igt_assert(rc6_residency >= pre_mmio_residency[0]); + igt_assert(rc6p_residency >= pre_mmio_residency[1]); + igt_assert(rc6_residency <= post_mmio_residency[0]); + igt_assert(rc6p_residency <= post_mmio_residency[1]); + } + } +} + +static void +test_perf_oa_mmio(void) +{ + uint64_t properties[] = { + /* Include OA reports in samples */ + DRM_I915_PERF_PROP_SAMPLE_OA, true, + + /* OA unit configuration */ + DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id, + DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format, + DRM_I915_PERF_PROP_OA_EXPONENT, oa_exp_1_millisec, + + /* CS parameters */ + DRM_I915_PERF_PROP_ENGINE, I915_EXEC_RENDER, + DRM_I915_PERF_PROP_SAMPLE_MMIO, 0, + }; + struct drm_i915_perf_open_param param = { + .flags = I915_PERF_FLAG_FD_CLOEXEC, + .num_properties = sizeof(properties) / 16, + .properties_ptr = to_user_pointer(properties), + }; + struct drm_i915_perf_mmio_list mmio; + + memset(&mmio, 0, sizeof(mmio)); + +#define GEN6_GT_GFX_RC6 0x138108 +#define GEN6_GT_GFX_RC6p 0x13810C + mmio.mmio_list[0] = GEN6_GT_GFX_RC6; + mmio.mmio_list[1] = GEN6_GT_GFX_RC6p; + mmio.num_mmio = 2; + + properties[ARRAY_SIZE(properties) - 1] = (uint64_t)&mmio; + + /* should be default, but just to be sure... */ + write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1); + + igt_fork(child, 1) { + int prop_size = ARRAY_SIZE(properties); + int num_reports = 10; + int report_size = get_perf_report_size(properties, prop_size, + test_oa_format); + int total_size = num_reports * report_size; + uint8_t *perf_reports = malloc(total_size); + uint64_t pre_mmio_residency[2], post_mmio_residency[2]; + + igt_assert(perf_reports); + + pre_mmio_residency[0] = read_debugfs_u64_record(drm_fd, + "i915_drpc_info", + "RC6 residency since boot"); + pre_mmio_residency[1] = read_debugfs_u64_record(drm_fd, + "i915_drpc_info", + "RC6+ residency since boot"); + perf_stream_capture_workload_samples(¶m, perf_reports, + num_reports, report_size, + NULL); + post_mmio_residency[0] = read_debugfs_u64_record(drm_fd, + "i915_drpc_info", + "RC6 residency since boot"); + post_mmio_residency[1] = read_debugfs_u64_record(drm_fd, + "i915_drpc_info", + "RC6+ residency since boot"); + verify_oa_mmio(perf_reports, num_reports, report_size, + pre_mmio_residency, post_mmio_residency); + free(perf_reports); + } + + igt_waitchildren(); +} + +struct ts_mmio_sample { + uint64_t ts; + uint32_t mmio[2]; +}; + +static void +verify_ts_mmio(uint8_t *perf_reports, int num_reports, size_t report_size, + uint64_t *pre_mmio_residency, uint64_t *post_mmio_residency) +{ + struct ts_mmio_sample *sample; + uint64_t rc6_residency; + uint64_t rc6p_residency; + + igt_debug("pre rc6 residency = %lu, rc6p residency = %lu, " + "post rc6 residency = %lu, rc6p residency = %lu\n", + pre_mmio_residency[0], pre_mmio_residency[1], + post_mmio_residency[0], post_mmio_residency[1]); + + for (int i = 0; i < num_reports; i++) { + size_t offset = i * report_size; + + sample = (struct ts_mmio_sample *) (perf_reports + offset); + + rc6_residency = intel_rc6_residency_us(sample->mmio[0]); + rc6p_residency = intel_rc6_residency_us(sample->mmio[1]); + + igt_debug("read mmio: rc6 = %u, rc6 residency = %lu, " + "rc6p = %u, rc6p residency = %lu\n", + sample->mmio[0], rc6_residency, + sample->mmio[1], rc6p_residency); + + igt_debug("read report: timestamp = %lu\n", sample->ts); + + igt_assert(rc6_residency >= pre_mmio_residency[0]); + igt_assert(rc6p_residency >= pre_mmio_residency[1]); + igt_assert(rc6_residency <= post_mmio_residency[0]); + igt_assert(rc6p_residency <= post_mmio_residency[1]); + } +} + +static void +test_perf_ts_mmio(void) +{ + uint64_t properties[] = { + /* CS parameters */ + DRM_I915_PERF_PROP_ENGINE, I915_EXEC_RENDER, + DRM_I915_PERF_PROP_SAMPLE_TS, true, + DRM_I915_PERF_PROP_SAMPLE_MMIO, 0, + }; + struct drm_i915_perf_open_param param = { + .flags = I915_PERF_FLAG_FD_CLOEXEC, + .num_properties = sizeof(properties) / 16, + .properties_ptr = to_user_pointer(properties), + }; + struct drm_i915_perf_mmio_list mmio; + + memset(&mmio, 0, sizeof(mmio)); + +#define GEN6_GT_GFX_RC6 0x138108 +#define GEN6_GT_GFX_RC6p 0x13810C + mmio.mmio_list[0] = GEN6_GT_GFX_RC6; + mmio.mmio_list[1] = GEN6_GT_GFX_RC6p; + mmio.num_mmio = 2; + + properties[ARRAY_SIZE(properties) - 1] = (uint64_t)&mmio; + + /* should be default, but just to be sure... */ + write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1); + + igt_fork(child, 1) { + int prop_size = ARRAY_SIZE(properties); + int num_reports = 2; + int report_size = get_perf_report_size_nonoa(properties, + prop_size); + int total_size = num_reports * report_size; + uint8_t *perf_reports = malloc(total_size); + uint64_t pre_mmio_residency[2], post_mmio_residency[2]; + + igt_assert(perf_reports); + + pre_mmio_residency[0] = read_debugfs_u64_record(drm_fd, + "i915_drpc_info", + "RC6 residency since boot"); + pre_mmio_residency[1] = read_debugfs_u64_record(drm_fd, + "i915_drpc_info", + "RC6+ residency since boot"); + perf_stream_capture_workload_samples(¶m, perf_reports, + num_reports, report_size, + NULL); + post_mmio_residency[0] = read_debugfs_u64_record(drm_fd, + "i915_drpc_info", + "RC6 residency since boot"); + post_mmio_residency[1] = read_debugfs_u64_record(drm_fd, + "i915_drpc_info", + "RC6+ residency since boot"); + verify_ts_mmio(perf_reports, num_reports, report_size, + pre_mmio_residency, post_mmio_residency); + free(perf_reports); + } + + igt_waitchildren(); +} + igt_main { igt_skip_on_simulation(); @@ -1171,6 +1456,12 @@ igt_main igt_subtest("perf-ts") test_perf_ts(); + igt_subtest("perf-mmio") { + igt_require(intel_get_device_info(devid)->gen >= 9); + test_perf_ts_mmio(); + test_perf_oa_mmio(); + } + igt_fixture { close(drm_fd); }