From patchwork Mon Sep 11 12:28:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juha-Pekka Heikkila X-Patchwork-Id: 9947293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 94E5F602C9 for ; Mon, 11 Sep 2017 12:29:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7743528BDC for ; Mon, 11 Sep 2017 12:29:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6C36F28BE6; Mon, 11 Sep 2017 12:29:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D401F28BDC for ; Mon, 11 Sep 2017 12:29:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD3156E39F; Mon, 11 Sep 2017 12:29:14 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id D36C36E397 for ; Mon, 11 Sep 2017 12:29:13 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id p17so6750484wmd.3 for ; Mon, 11 Sep 2017 05:29:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Gm4urx8+BNqClDIPWvu5N6eTK/P6XdoH6r+ZRv5lLyw=; b=Bg13m7MDf23idxG3kSOpF+aWlgSb39X9zk2eP8uwULKC1WLXcJesZ9+xzcNOoT9oWP thvT0S9/AYJiXHO+hW59XkuGLttMyfhmqa1fJTWnlO2q02MNclyHOQH9FS6JfWTFEUQp 5xPYE+i7WqfwT+GxexcXPjUcLINo+21AZCCujLLBg6anLTBdGzSlQ9TYwqy5B+B12r/A IwgypTfIig4/K34R5MKK4jtGdDbHI+lRCGTttxMRyHshUhMEcXUgio8t2lgh6zmbkblQ 1Co5D92EgUs5O2Phz0B4sHAYR+A4JPFE/C9O0Yvvc4ulBksvakqG4aTGkHA/t0TL5jTT hN1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Gm4urx8+BNqClDIPWvu5N6eTK/P6XdoH6r+ZRv5lLyw=; b=F/Tk8c0wf2rvLHYN+IjOAPADyu1fV9oUixKXiQhBx1tyFLhsjY0eVXnefXgRmdqAX3 BQPnm2stNUEWWbg0TvZs6/SPWHHzWSZ6g0sT8fxuDb3Aw7RWCfYKQ/0OgIciAsffkiQf Mb17+AJ4HjeBjAw2cdDwsEFsS4ByiQLmtC/caNFhj5fvxyzkxW4/MJp7kR4W2vVQY1dl 74SRdN1QgaNP5w6dB2agLeCSP+M1y2H9+akI/6FCsbJXTAJ6ZS4H7M+zzVXDjD2VLd3O WBsfod1xFCj4lO/gz2X/gskHGOcXnOiV56snvAcTSK/d43QwvtUx181lcne6fDfjhoIf aHpQ== X-Gm-Message-State: AHPjjUh2iunMjtU/kdubIsKEE9lJwjJnJbXDfA3EQIpC8yEyhAeP/oXr nlkCf0ICrSI8WwwB X-Google-Smtp-Source: ADKCNb52bKhQI2Qj1o30o4xxaqpz6ozN2+XMI23WVRcp2bAYMdo+QW/SKgSNpfBtXNioVwyBJpe7yg== X-Received: by 10.80.187.46 with SMTP id y43mr9490113ede.137.1505132952186; Mon, 11 Sep 2017 05:29:12 -0700 (PDT) Received: from jheikkil-MOBL1.fi.intel.com ([2001:998:22:0:90d4:903f:9739:d412]) by smtp.gmail.com with ESMTPSA id t49sm1425111edd.62.2017.09.11.05.29.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 Sep 2017 05:29:11 -0700 (PDT) From: Juha-Pekka Heikkila To: intel-gfx@lists.freedesktop.org Date: Mon, 11 Sep 2017 15:28:56 +0300 Message-Id: <1505132937-27327-3-git-send-email-juhapekka.heikkila@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505132937-27327-1-git-send-email-juhapekka.heikkila@gmail.com> References: <1505132937-27327-1-git-send-email-juhapekka.heikkila@gmail.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Unify skylake plane update X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Don't handle skylake primary plane separately as it is similar plane as the others. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/i915_drv.h | 8 ++++ drivers/gpu/drm/i915/intel_display.c | 85 +----------------------------------- drivers/gpu/drm/i915/intel_drv.h | 9 ++-- drivers/gpu/drm/i915/intel_fbc.c | 11 +++-- drivers/gpu/drm/i915/intel_sprite.c | 2 +- 5 files changed, 22 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8352cbe..2f96286 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1077,6 +1077,14 @@ struct intel_fbc { int src_w; int src_h; bool visible; + /* + * Display surface base address adjustement for + * pageflips. Note that on gen4+ this only adjusts up + * to a tile, offsets within a tile are handled in + * the hw itself (with the TILEOFF register). + */ + int adjusted_x; + int adjusted_y; } plane; struct { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f922e2f..ac4073a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3278,7 +3278,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, const struct intel_plane_state *plane_state) { struct drm_i915_private *dev_priv = to_i915(primary->base.dev); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); const struct drm_framebuffer *fb = plane_state->base.fb; enum plane plane = primary->plane; u32 linear_offset; @@ -3296,9 +3295,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, else dspaddr_offset = linear_offset; - crtc->adjusted_x = x; - crtc->adjusted_y = y; - spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); if (INTEL_GEN(dev_priv) < 4) { @@ -3534,83 +3530,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, return plane_ctl; } -static void skylake_update_primary_plane(struct intel_plane *plane, - const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) -{ - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); - const struct drm_framebuffer *fb = plane_state->base.fb; - enum plane_id plane_id = plane->id; - enum pipe pipe = plane->pipe; - u32 plane_ctl = plane_state->ctl; - unsigned int rotation = plane_state->base.rotation; - u32 stride = skl_plane_stride(fb, 0, rotation); - u32 aux_stride = skl_plane_stride(fb, 1, rotation); - u32 surf_addr = plane_state->main.offset; - int scaler_id = plane_state->scaler_id; - int src_x = plane_state->main.x; - int src_y = plane_state->main.y; - int src_w = drm_rect_width(&plane_state->base.src) >> 16; - int src_h = drm_rect_height(&plane_state->base.src) >> 16; - int dst_x = plane_state->base.dst.x1; - int dst_y = plane_state->base.dst.y1; - int dst_w = drm_rect_width(&plane_state->base.dst); - int dst_h = drm_rect_height(&plane_state->base.dst); - unsigned long irqflags; - - /* Sizes are 0 based */ - src_w--; - src_h--; - dst_w--; - dst_h--; - - crtc->dspaddr_offset = surf_addr; - - crtc->adjusted_x = src_x; - crtc->adjusted_y = src_y; - - spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { - I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), - PLANE_COLOR_PIPE_GAMMA_ENABLE | - PLANE_COLOR_PIPE_CSC_ENABLE | - PLANE_COLOR_PLANE_GAMMA_DISABLE); - } - - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); - I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); - I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); - I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); - I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), - (plane_state->aux.offset - surf_addr) | aux_stride); - I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), - (plane_state->aux.y << 16) | plane_state->aux.x); - - if (scaler_id >= 0) { - uint32_t ps_ctrl = 0; - - WARN_ON(!dst_w || !dst_h); - ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | - crtc_state->scaler_state.scalers[scaler_id].mode; - I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); - I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); - I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); - I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); - I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); - } else { - I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); - } - - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); - - POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); - - spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); -} - static void skylake_disable_primary_plane(struct intel_plane *primary, struct intel_crtc *crtc) { @@ -13265,7 +13184,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) num_formats = ARRAY_SIZE(skl_primary_formats); modifiers = skl_format_modifiers_ccs; - primary->update_plane = skylake_update_primary_plane; + primary->update_plane = skl_update_plane; primary->disable_plane = skylake_disable_primary_plane; } else if (INTEL_GEN(dev_priv) >= 9) { intel_primary_formats = skl_primary_formats; @@ -13275,7 +13194,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) else modifiers = skl_format_modifiers_noccs; - primary->update_plane = skylake_update_primary_plane; + primary->update_plane = skl_update_plane; primary->disable_plane = skylake_disable_primary_plane; } else if (INTEL_GEN(dev_priv) >= 4) { intel_primary_formats = i965_primary_formats; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 0d0abed1..d932613 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -802,12 +802,6 @@ struct intel_crtc { unsigned long long enabled_power_domains; struct intel_overlay *overlay; - /* Display surface base address adjustement for pageflips. Note that on - * gen4+ this only adjusts up to a tile, offsets within a tile are - * handled in the hw itself (with the TILEOFF register). */ - int adjusted_x; - int adjusted_y; - struct intel_crtc_state *config; /* global reset count when the last flip was submitted */ @@ -1887,6 +1881,9 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); void intel_pipe_update_start(struct intel_crtc *crtc); void intel_pipe_update_end(struct intel_crtc *crtc); +void skl_update_plane(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state); /* intel_tv.c */ void intel_tv_init(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 58a772d..dc059808 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) */ static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) { - return crtc->base.y - crtc->adjusted_y; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_fbc *fbc = &dev_priv->fbc; + + return crtc->base.y - fbc->state_cache.plane.adjusted_y; } /* @@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w, &effective_h); - effective_w += crtc->adjusted_x; - effective_h += crtc->adjusted_y; + effective_w += fbc->state_cache.plane.adjusted_x; + effective_h += fbc->state_cache.plane.adjusted_y; return effective_w <= max_w && effective_h <= max_h; } @@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16; cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16; cache->plane.visible = plane_state->base.visible; + cache->plane.adjusted_x = plane_state->main.x; + cache->plane.adjusted_y = plane_state->main.y; if (!cache->plane.visible) return; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 524933b..ef16519 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -225,7 +225,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc) #endif } -static void +void skl_update_plane(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state)