From patchwork Thu Sep 14 09:55:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9952665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9C44B60317 for ; Thu, 14 Sep 2017 09:52:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B40D251F4 for ; Thu, 14 Sep 2017 09:52:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6D7D928E04; Thu, 14 Sep 2017 09:52:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C91BF289E1 for ; Thu, 14 Sep 2017 09:52:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DFD6F6E9E3; Thu, 14 Sep 2017 09:52:04 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 608E56E9E0 for ; Thu, 14 Sep 2017 09:52:03 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Sep 2017 02:51:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,392,1500966000"; d="scan'208";a="311578634" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by fmsmga004.fm.intel.com with ESMTP; 14 Sep 2017 02:51:47 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Sep 2017 15:25:05 +0530 Message-Id: <1505382908-6844-4-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505382908-6844-1-git-send-email-sagar.a.kamble@intel.com> References: <1505382908-6844-1-git-send-email-sagar.a.kamble@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/guc: Fix GuC interaction in reset/suspend scenarios X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: "Kamble, Sagar A" guc_ggtt_invalidate/guc_interrupts/guc_communication should be disabled towards end of reset/suspend post GuC suspension as these are setup back again during recovery/resume. Prepared helpers intel_guc_pause and intel_guc_unpause that will do teardown/bringup of this setup along with suspension/resumption of GuC if loaded. These helpers can then be used along the system or runtime suspend/resume paths as applicable. Currently post system resume, since GuC is loaded completely system_resume function for GuC is doing nothing. We rely on the setup happening in intel_uc_init_hw path. During runtim_suspend we will call intel_guc_pause helper that will suspend GuC operation by sending Host to GuC action ENTER_S_STATE and then disable ggtt_invalidate, disable GuC communication, disable GuC interrupts. Another helper added is intel_guc_reset_prepare, this will make sure that disabling of ggtt_invalidate, communication and GuC interrupts happens prior to reset and updates the firmware load status to PENDING. This is applicable in case of full GPU reset though. v2: Updated commit message. Added note about skipped call to intel_guc_system_resume. guc_enable/disable_communication was moved to earlier patch so corresponding rebase. (Michal Wajdeczko) Cc: Chris Wilson Cc: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Michał Winiarski Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_drv.c | 11 ++- drivers/gpu/drm/i915/i915_gem.c | 4 +- drivers/gpu/drm/i915/i915_guc_submission.c | 50 ----------- drivers/gpu/drm/i915/intel_guc.c | 131 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc.h | 7 +- 5 files changed, 146 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b825024..d70a160 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1683,6 +1683,11 @@ static int i915_drm_resume(struct drm_device *dev) drm_mode_config_reset(dev); + /* + * NB: Full gem reinitialization is being done during i915_drm_resume, + * hence intel_guc_system_resume will be of no use. If full + * reinitialization is avoided, need to call intel_guc_system_resume. + */ mutex_lock(&dev->struct_mutex); if (i915_gem_init_hw(dev_priv)) { DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); @@ -1690,8 +1695,6 @@ static int i915_drm_resume(struct drm_device *dev) } mutex_unlock(&dev->struct_mutex); - intel_guc_resume(&dev_priv->guc); - intel_modeset_init_hw(dev); spin_lock_irq(&dev_priv->irq_lock); @@ -2492,7 +2495,7 @@ static int intel_runtime_suspend(struct device *kdev) */ i915_gem_runtime_suspend(dev_priv); - intel_guc_suspend(&dev_priv->guc); + intel_guc_runtime_suspend(&dev_priv->guc); intel_runtime_pm_disable_interrupts(dev_priv); @@ -2577,7 +2580,7 @@ static int intel_runtime_resume(struct device *kdev) if (intel_uncore_unclaimed_mmio(dev_priv)) DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); - intel_guc_resume(&dev_priv->guc); + intel_guc_runtime_resume(&dev_priv->guc); if (IS_GEN9_LP(dev_priv)) { bxt_disable_dc9(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index eb20e73..306e42a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2847,6 +2847,8 @@ int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) i915_gem_revoke_fences(dev_priv); + intel_guc_reset_prepare(&dev_priv->guc); + return err; } @@ -4575,7 +4577,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) i915_gem_contexts_lost(dev_priv); mutex_unlock(&dev->struct_mutex); - intel_guc_suspend(&dev_priv->guc); + intel_guc_system_suspend(&dev_priv->guc); cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); cancel_delayed_work_sync(&dev_priv->gt.retire_work); diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index c9838e0..154cee7 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -1204,53 +1204,3 @@ void i915_guc_submission_disable(struct drm_i915_private *dev_priv) guc_client_free(guc->execbuf_client); guc->execbuf_client = NULL; } - -/** - * intel_guc_suspend() - notify GuC entering suspend state - */ -int intel_guc_suspend(struct intel_guc *guc) -{ - struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct i915_gem_context *ctx; - u32 data[3]; - - if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) - return 0; - - gen9_disable_guc_interrupts(dev_priv); - - ctx = dev_priv->kernel_context; - - data[0] = INTEL_GUC_ACTION_ENTER_S_STATE; - /* any value greater than GUC_POWER_D0 */ - data[1] = GUC_POWER_D1; - /* first page is shared data with GuC */ - data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN * PAGE_SIZE; - - return intel_guc_send(guc, data, ARRAY_SIZE(data)); -} - -/** - * intel_guc_resume() - notify GuC resuming from suspend state - */ -int intel_guc_resume(struct intel_guc *guc) -{ - struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct i915_gem_context *ctx; - u32 data[3]; - - if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) - return 0; - - if (i915.guc_log_level >= 0) - gen9_enable_guc_interrupts(dev_priv); - - ctx = dev_priv->kernel_context; - - data[0] = INTEL_GUC_ACTION_EXIT_S_STATE; - data[1] = GUC_POWER_D0; - /* first page is shared data with GuC */ - data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN * PAGE_SIZE; - - return intel_guc_send(guc, data, ARRAY_SIZE(data)); -} diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 75bb830..b957dab 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -202,3 +202,134 @@ void intel_guc_disable_communication(struct intel_guc *guc) guc->send = intel_guc_send_nop; } + +/** + * intel_guc_suspend() - notify GuC entering suspend state + */ +static int intel_guc_suspend(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + struct i915_gem_context *ctx; + u32 data[3]; + + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) + return 0; + + ctx = dev_priv->kernel_context; + + data[0] = INTEL_GUC_ACTION_ENTER_S_STATE; + /* any value greater than GUC_POWER_D0 */ + data[1] = GUC_POWER_D1; + /* first page is shared data with GuC */ + data[2] = guc_ggtt_offset(ctx->engine[RCS].state); + + return intel_guc_send(guc, data, ARRAY_SIZE(data)); +} + +/** + * intel_guc_resume() - notify GuC resuming from suspend state + */ +static int intel_guc_resume(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + struct i915_gem_context *ctx; + u32 data[3]; + + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) + return 0; + + ctx = dev_priv->kernel_context; + + data[0] = INTEL_GUC_ACTION_EXIT_S_STATE; + data[1] = GUC_POWER_D0; + /* first page is shared data with GuC */ + data[2] = guc_ggtt_offset(ctx->engine[RCS].state); + + return intel_guc_send(guc, data, ARRAY_SIZE(data)); +} + +static void intel_guc_sanitize(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + + i915_ggtt_disable_guc(dev_priv); + intel_guc_disable_communication(guc); + gen9_disable_guc_interrupts(dev_priv); +} + +void intel_guc_reset_prepare(struct intel_guc *guc) +{ + if (!i915.enable_guc_loading) + return; + + intel_guc_sanitize(guc); + guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING; +} + +static int intel_guc_pause(struct intel_guc *guc) +{ + int ret = 0; + + ret = intel_guc_suspend(guc); + intel_guc_sanitize(guc); + + return ret; +} + +static int intel_guc_unpause(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + int ret = 0; + + if (i915.guc_log_level >= 0) + gen9_enable_guc_interrupts(dev_priv); + intel_guc_enable_communication(guc); + i915_ggtt_enable_guc(dev_priv); + ret = intel_guc_resume(guc); + + return ret; +} + +int intel_guc_runtime_suspend(struct intel_guc *guc) +{ + if (!i915.enable_guc_loading) + return 0; + + return intel_guc_pause(guc); +} + +int intel_guc_runtime_resume(struct intel_guc *guc) +{ + if (!i915.enable_guc_loading) + return 0; + + return intel_guc_unpause(guc); +} + +int intel_guc_system_suspend(struct intel_guc *guc) +{ + int ret = 0; + + if (!i915.enable_guc_loading) + return ret; + + ret = intel_guc_pause(guc); + guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING; + + return ret; +} + +int intel_guc_system_resume(struct intel_guc *guc) +{ + int ret = 0; + + if (!i915.enable_guc_loading) + return ret; + + /* + * Placeholder for GuC resume from system suspend/freeze states. + * Currently full reinitialization of GEM and GuC happens along + * these paths, Hence this function is doing nothing. + */ + return ret; +} diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 8ed0e81..4d4e344 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -151,6 +151,11 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) void intel_guc_auth_huc(struct intel_guc *guc, struct intel_huc *huc); int intel_guc_enable_communication(struct intel_guc *guc); void intel_guc_disable_communication(struct intel_guc *guc); +void intel_guc_reset_prepare(struct intel_guc *guc); +int intel_guc_runtime_suspend(struct intel_guc *guc); +int intel_guc_runtime_resume(struct intel_guc *guc); +int intel_guc_system_suspend(struct intel_guc *guc); +int intel_guc_system_resume(struct intel_guc *guc); /* intel_guc_loader.c */ int intel_guc_select_fw(struct intel_guc *guc); @@ -163,8 +168,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) void i915_guc_submission_disable(struct drm_i915_private *dev_priv); void i915_guc_submission_fini(struct drm_i915_private *dev_priv); struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); -int intel_guc_suspend(struct intel_guc *guc); -int intel_guc_resume(struct intel_guc *guc); /* intel_guc_log.c */ int intel_guc_log_create(struct intel_guc *guc);