From patchwork Thu Sep 14 12:12:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Srinivas, Vidya" X-Patchwork-Id: 9952925 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0643560317 for ; Thu, 14 Sep 2017 12:03:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EEA5828F78 for ; Thu, 14 Sep 2017 12:03:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E3C0F28FCC; Thu, 14 Sep 2017 12:03:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9706D28F78 for ; Thu, 14 Sep 2017 12:03:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 261566EA6B; Thu, 14 Sep 2017 12:03:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id E9F2B6EA6B for ; Thu, 14 Sep 2017 12:03:37 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Sep 2017 05:03:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.42,392,1500966000"; d="scan'208"; a="1195023995" Received: from vsrini4-ubuntu-intel.iind.intel.com ([10.223.25.59]) by fmsmga001.fm.intel.com with ESMTP; 14 Sep 2017 05:03:30 -0700 From: Vidya Srinivas To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Sep 2017 17:42:02 +0530 Message-Id: <1505391122-9437-2-git-send-email-vidya.srinivas@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505391122-9437-1-git-send-email-vidya.srinivas@intel.com> References: <1505391122-9437-1-git-send-email-vidya.srinivas@intel.com> MIME-Version: 1.0 Cc: Vidya Srinivas Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Control Vblank through IER instead of IMR X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Uma Shankar Frame timestamp register is not updated if the vblank inteerupts are not unmasked. This is needed to calculate scanlines for DSI encoders. This patch changes the vblank enable/disable logic by controlling it through Pipe IER register instead of IMR. Pipe IMR will be unmasked permanently and IER will be toggled based on need. Credits-to: Ville Syrjälä Signed-off-by: Uma Shankar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 47668dd..a417cea 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -498,15 +498,14 @@ void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, if (WARN_ON(!intel_irqs_enabled(dev_priv))) return; - new_val = dev_priv->de_irq_mask[pipe]; - new_val &= ~interrupt_mask; - new_val |= (~enabled_irq_mask & interrupt_mask); + new_val = I915_READ(GEN8_DE_PIPE_IER(pipe)); + if (enabled_irq_mask) + new_val |= enabled_irq_mask; + else + new_val &= ~interrupt_mask; - if (new_val != dev_priv->de_irq_mask[pipe]) { - dev_priv->de_irq_mask[pipe] = new_val; - I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); - POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); - } + I915_WRITE(GEN8_DE_PIPE_IER(pipe), new_val); + POSTING_READ(GEN8_DE_PIPE_IER(pipe)); } /** @@ -3450,8 +3449,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) GEN8_DE_PIPE_IRQ_FAULT_ERRORS; } - de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | - GEN8_PIPE_FIFO_UNDERRUN; + de_pipe_enables = de_pipe_masked | GEN8_PIPE_FIFO_UNDERRUN; + + de_pipe_masked |= GEN8_PIPE_VBLANK; de_port_enables = de_port_masked; if (IS_GEN9_LP(dev_priv))