| Message ID | 1505650654-11091-4-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, 17 Sep 2017 14:17:28 +0200, Sagar Arun Kamble <sagar.a.kamble@intel.com> wrote: Maybe to make this refactoring series much clearer you should start with this patch ? and btw, please don't forget about adding commit description. > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Michał Winiarski <michal.winiarski@intel.com> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_guc.h | 126 > +++++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_uc.h | 125 > -------------------------------------- > 3 files changed, 127 insertions(+), 125 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h > index 5aecbf7..b0f38bb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -59,6 +59,7 @@ > #include "intel_bios.h" > #include "intel_dpll_mgr.h" > #include "intel_uc.h" > +#include "intel_guc.h" Hmm, the goal of previous (unfinished) refactoring was to wrap all details about Guc/Huc into generic single "uc" component. Thus any "guc"/"huc" specific headers shall be included by master "intel_uc.h". If this is hard to make, then maybe we should postpone changes in .h and current limit refactoring only to .c files. Michal > #include "intel_lrc.h" > #include "intel_ringbuffer.h" > diff --git a/drivers/gpu/drm/i915/intel_guc.h > b/drivers/gpu/drm/i915/intel_guc.h > index 06f2d27..919b6e1 100644 > --- a/drivers/gpu/drm/i915/intel_guc.h > +++ b/drivers/gpu/drm/i915/intel_guc.h > @@ -24,6 +24,102 @@ > #ifndef _INTEL_GUC_H_ > #define _INTEL_GUC_H_ > +/* > + * This structure primarily describes the GEM object shared with the > GuC. > + * The specs sometimes refer to this object as a "GuC context", but we > use > + * the term "client" to avoid confusion with hardware contexts. This > + * GEM object is held for the entire lifetime of our interaction with > + * the GuC, being allocated before the GuC is loaded with its firmware. > + * Because there's no way to update the address used by the GuC after > + * initialisation, the shared object must stay pinned into the GGTT as > + * long as the GuC is in use. We also keep the first page (only) mapped > + * into kernel address space, as it includes shared data that must be > + * updated on every request submission. > + * > + * The single GEM object described here is actually made up of several > + * separate areas, as far as the GuC is concerned. The first page (kept > + * kmap'd) includes the "process descriptor" which holds sequence data > for > + * the doorbell, and one cacheline which actually *is* the doorbell; a > + * write to this will "ring the doorbell" (i.e. send an interrupt to the > + * GuC). The subsequent pages of the client object constitute the work > + * queue (a circular array of work items), again described in the > process > + * descriptor. Work queue pages are mapped momentarily as required. > + */ > +struct i915_guc_client { > + struct i915_vma *vma; > + void *vaddr; > + struct i915_gem_context *owner; > + struct intel_guc *guc; > + > + uint32_t engines; /* bitmap of (host) engine ids */ > + uint32_t priority; > + u32 stage_id; > + uint32_t proc_desc_offset; > + > + u16 doorbell_id; > + unsigned long doorbell_offset; > + > + spinlock_t wq_lock; > + /* Per-engine counts of GuC submissions */ > + uint64_t submissions[I915_NUM_ENGINES]; > +}; > + > +struct intel_guc_log { > + uint32_t flags; > + struct i915_vma *vma; > + /* The runtime stuff gets created only when GuC logging gets enabled */ > + struct { > + void *buf_addr; > + struct workqueue_struct *flush_wq; > + struct work_struct flush_work; > + struct rchan *relay_chan; > + } runtime; > + /* logging related stats */ > + u32 capture_miss_count; > + u32 flush_interrupt_count; > + u32 prev_overflow_count[GUC_MAX_LOG_BUFFER]; > + u32 total_overflow_count[GUC_MAX_LOG_BUFFER]; > + u32 flush_count[GUC_MAX_LOG_BUFFER]; > +}; > + > +struct intel_guc { > + struct intel_uc_fw fw; > + struct intel_guc_log log; > + struct intel_guc_ct ct; > + > + /* Log snapshot if GuC errors during load */ > + struct drm_i915_gem_object *load_err_log; > + > + /* intel_guc_recv interrupt related state */ > + bool interrupts_enabled; > + > + struct i915_vma *ads_vma; > + struct i915_vma *stage_desc_pool; > + void *stage_desc_pool_vaddr; > + struct ida stage_ids; > + > + struct i915_guc_client *execbuf_client; > + > + DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); > + uint32_t db_cacheline; /* Cyclic counter mod pagesize */ > + > + /* GuC's FW specific registers used in MMIO send */ > + struct { > + u32 base; > + unsigned int count; > + enum forcewake_domains fw_domains; > + } send_regs; > + > + /* To serialize the intel_guc_send actions */ > + struct mutex send_mutex; > + > + /* GuC's FW specific send function */ > + int (*send)(struct intel_guc *guc, const u32 *data, u32 len); > + > + /* GuC's FW specific notify function */ > + void (*notify)(struct intel_guc *guc); > +}; > + > static inline int intel_guc_send(struct intel_guc *guc, > const u32 *action, > u32 len) > @@ -36,6 +132,15 @@ static inline void intel_guc_notify(struct intel_guc > *guc) > guc->notify(guc); > } > +static inline u32 guc_ggtt_offset(struct i915_vma *vma) > +{ > + u32 offset = i915_ggtt_offset(vma); > + > + GEM_BUG_ON(offset < GUC_WOPCM_TOP); > + GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); > + return offset; > +} > + > /* intel_guc.c */ > int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 > len); > void intel_guc_init_early(struct intel_guc *guc); > @@ -43,4 +148,25 @@ static inline void intel_guc_notify(struct intel_guc > *guc) > int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 > len); > int intel_guc_sample_forcewake(struct intel_guc *guc); > +/* intel_guc_loader.c */ > +int intel_guc_select_fw(struct intel_guc *guc); > +int intel_guc_init_hw(struct intel_guc *guc); > +int intel_guc_suspend(struct drm_i915_private *dev_priv); > +int intel_guc_resume(struct drm_i915_private *dev_priv); > +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv); > + > +/* i915_guc_submission.c */ > +int i915_guc_submission_init(struct drm_i915_private *dev_priv); > +int i915_guc_submission_enable(struct drm_i915_private *dev_priv); > +void i915_guc_submission_disable(struct drm_i915_private *dev_priv); > +void i915_guc_submission_fini(struct drm_i915_private *dev_priv); > +struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 > size); > + > +/* intel_guc_log.c */ > +int intel_guc_log_create(struct intel_guc *guc); > +void intel_guc_log_destroy(struct intel_guc *guc); > +int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 > control_val); > +void i915_guc_log_register(struct drm_i915_private *dev_priv); > +void i915_guc_log_unregister(struct drm_i915_private *dev_priv); > + > #endif > diff --git a/drivers/gpu/drm/i915/intel_uc.h > b/drivers/gpu/drm/i915/intel_uc.h > index 2c11d11..30902f3 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -32,46 +32,6 @@ > struct drm_i915_gem_request; > -/* > - * This structure primarily describes the GEM object shared with the > GuC. > - * The specs sometimes refer to this object as a "GuC context", but we > use > - * the term "client" to avoid confusion with hardware contexts. This > - * GEM object is held for the entire lifetime of our interaction with > - * the GuC, being allocated before the GuC is loaded with its firmware. > - * Because there's no way to update the address used by the GuC after > - * initialisation, the shared object must stay pinned into the GGTT as > - * long as the GuC is in use. We also keep the first page (only) mapped > - * into kernel address space, as it includes shared data that must be > - * updated on every request submission. > - * > - * The single GEM object described here is actually made up of several > - * separate areas, as far as the GuC is concerned. The first page (kept > - * kmap'd) includes the "process descriptor" which holds sequence data > for > - * the doorbell, and one cacheline which actually *is* the doorbell; a > - * write to this will "ring the doorbell" (i.e. send an interrupt to the > - * GuC). The subsequent pages of the client object constitute the work > - * queue (a circular array of work items), again described in the > process > - * descriptor. Work queue pages are mapped momentarily as required. > - */ > -struct i915_guc_client { > - struct i915_vma *vma; > - void *vaddr; > - struct i915_gem_context *owner; > - struct intel_guc *guc; > - > - uint32_t engines; /* bitmap of (host) engine ids */ > - uint32_t priority; > - u32 stage_id; > - uint32_t proc_desc_offset; > - > - u16 doorbell_id; > - unsigned long doorbell_offset; > - > - spinlock_t wq_lock; > - /* Per-engine counts of GuC submissions */ > - uint64_t submissions[I915_NUM_ENGINES]; > -}; > - > enum intel_uc_fw_status { > INTEL_UC_FIRMWARE_FAIL = -1, > INTEL_UC_FIRMWARE_NONE = 0, > @@ -138,62 +98,6 @@ struct intel_uc_fw { > uint32_t ucode_offset; > }; > -struct intel_guc_log { > - uint32_t flags; > - struct i915_vma *vma; > - /* The runtime stuff gets created only when GuC logging gets enabled */ > - struct { > - void *buf_addr; > - struct workqueue_struct *flush_wq; > - struct work_struct flush_work; > - struct rchan *relay_chan; > - } runtime; > - /* logging related stats */ > - u32 capture_miss_count; > - u32 flush_interrupt_count; > - u32 prev_overflow_count[GUC_MAX_LOG_BUFFER]; > - u32 total_overflow_count[GUC_MAX_LOG_BUFFER]; > - u32 flush_count[GUC_MAX_LOG_BUFFER]; > -}; > - > -struct intel_guc { > - struct intel_uc_fw fw; > - struct intel_guc_log log; > - struct intel_guc_ct ct; > - > - /* Log snapshot if GuC errors during load */ > - struct drm_i915_gem_object *load_err_log; > - > - /* intel_guc_recv interrupt related state */ > - bool interrupts_enabled; > - > - struct i915_vma *ads_vma; > - struct i915_vma *stage_desc_pool; > - void *stage_desc_pool_vaddr; > - struct ida stage_ids; > - > - struct i915_guc_client *execbuf_client; > - > - DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); > - uint32_t db_cacheline; /* Cyclic counter mod pagesize */ > - > - /* GuC's FW specific registers used in MMIO send */ > - struct { > - u32 base; > - unsigned int count; > - enum forcewake_domains fw_domains; > - } send_regs; > - > - /* To serialize the intel_guc_send actions */ > - struct mutex send_mutex; > - > - /* GuC's FW specific send function */ > - int (*send)(struct intel_guc *guc, const u32 *data, u32 len); > - > - /* GuC's FW specific notify function */ > - void (*notify)(struct intel_guc *guc); > -}; > - > struct intel_huc { > /* Generic uC firmware management */ > struct intel_uc_fw fw; > @@ -209,35 +113,6 @@ struct intel_huc { > int intel_uc_init_hw(struct drm_i915_private *dev_priv); > void intel_uc_fini_hw(struct drm_i915_private *dev_priv); > -/* intel_guc_loader.c */ > -int intel_guc_select_fw(struct intel_guc *guc); > -int intel_guc_init_hw(struct intel_guc *guc); > -int intel_guc_suspend(struct drm_i915_private *dev_priv); > -int intel_guc_resume(struct drm_i915_private *dev_priv); > -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv); > - > -/* i915_guc_submission.c */ > -int i915_guc_submission_init(struct drm_i915_private *dev_priv); > -int i915_guc_submission_enable(struct drm_i915_private *dev_priv); > -void i915_guc_submission_disable(struct drm_i915_private *dev_priv); > -void i915_guc_submission_fini(struct drm_i915_private *dev_priv); > -struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 > size); > - > -/* intel_guc_log.c */ > -int intel_guc_log_create(struct intel_guc *guc); > -void intel_guc_log_destroy(struct intel_guc *guc); > -int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 > control_val); > -void i915_guc_log_register(struct drm_i915_private *dev_priv); > -void i915_guc_log_unregister(struct drm_i915_private *dev_priv); > - > -static inline u32 guc_ggtt_offset(struct i915_vma *vma) > -{ > - u32 offset = i915_ggtt_offset(vma); > - GEM_BUG_ON(offset < GUC_WOPCM_TOP); > - GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); > - return offset; > -} > - > /* intel_huc.c */ > void intel_huc_select_fw(struct intel_huc *huc); > void intel_huc_init_hw(struct intel_huc *huc);
On 9/17/2017 11:54 PM, Michal Wajdeczko wrote: > On Sun, 17 Sep 2017 14:17:28 +0200, Sagar Arun Kamble > <sagar.a.kamble@intel.com> wrote: > > Maybe to make this refactoring series much clearer you should start > with this patch ? > and btw, please don't forget about adding commit description. Sorry. Will update the patch and reorder. Tend to think that change obvious from commit subject does not need the commit message. Will add commit message. > >> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> >> Cc: Michał Winiarski <michal.winiarski@intel.com> >> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 1 + >> drivers/gpu/drm/i915/intel_guc.h | 126 >> +++++++++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/i915/intel_uc.h | 125 >> -------------------------------------- >> 3 files changed, 127 insertions(+), 125 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h >> b/drivers/gpu/drm/i915/i915_drv.h >> index 5aecbf7..b0f38bb 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -59,6 +59,7 @@ >> #include "intel_bios.h" >> #include "intel_dpll_mgr.h" >> #include "intel_uc.h" >> +#include "intel_guc.h" > > Hmm, the goal of previous (unfinished) refactoring was to > wrap all details about Guc/Huc into generic single "uc" > component. Thus any "guc"/"huc" specific headers shall > be included by master "intel_uc.h". If this is hard to > make, then maybe we should postpone changes in .h and > current limit refactoring only to .c files. > > Michal Sure. I will limit the factoring only to .c files. > >> #include "intel_lrc.h" >> #include "intel_ringbuffer.h" >> diff --git a/drivers/gpu/drm/i915/intel_guc.h >> b/drivers/gpu/drm/i915/intel_guc.h >> index 06f2d27..919b6e1 100644 >> --- a/drivers/gpu/drm/i915/intel_guc.h >> +++ b/drivers/gpu/drm/i915/intel_guc.h >> @@ -24,6 +24,102 @@ >> #ifndef _INTEL_GUC_H_ >> #define _INTEL_GUC_H_ >> +/* >> + * This structure primarily describes the GEM object shared with the >> GuC. >> + * The specs sometimes refer to this object as a "GuC context", but >> we use >> + * the term "client" to avoid confusion with hardware contexts. This >> + * GEM object is held for the entire lifetime of our interaction with >> + * the GuC, being allocated before the GuC is loaded with its firmware. >> + * Because there's no way to update the address used by the GuC after >> + * initialisation, the shared object must stay pinned into the GGTT as >> + * long as the GuC is in use. We also keep the first page (only) mapped >> + * into kernel address space, as it includes shared data that must be >> + * updated on every request submission. >> + * >> + * The single GEM object described here is actually made up of several >> + * separate areas, as far as the GuC is concerned. The first page (kept >> + * kmap'd) includes the "process descriptor" which holds sequence >> data for >> + * the doorbell, and one cacheline which actually *is* the doorbell; a >> + * write to this will "ring the doorbell" (i.e. send an interrupt to >> the >> + * GuC). The subsequent pages of the client object constitute the work >> + * queue (a circular array of work items), again described in the >> process >> + * descriptor. Work queue pages are mapped momentarily as required. >> + */ >> +struct i915_guc_client { >> + struct i915_vma *vma; >> + void *vaddr; >> + struct i915_gem_context *owner; >> + struct intel_guc *guc; >> + >> + uint32_t engines; /* bitmap of (host) engine ids */ >> + uint32_t priority; >> + u32 stage_id; >> + uint32_t proc_desc_offset; >> + >> + u16 doorbell_id; >> + unsigned long doorbell_offset; >> + >> + spinlock_t wq_lock; >> + /* Per-engine counts of GuC submissions */ >> + uint64_t submissions[I915_NUM_ENGINES]; >> +}; >> + >> +struct intel_guc_log { >> + uint32_t flags; >> + struct i915_vma *vma; >> + /* The runtime stuff gets created only when GuC logging gets >> enabled */ >> + struct { >> + void *buf_addr; >> + struct workqueue_struct *flush_wq; >> + struct work_struct flush_work; >> + struct rchan *relay_chan; >> + } runtime; >> + /* logging related stats */ >> + u32 capture_miss_count; >> + u32 flush_interrupt_count; >> + u32 prev_overflow_count[GUC_MAX_LOG_BUFFER]; >> + u32 total_overflow_count[GUC_MAX_LOG_BUFFER]; >> + u32 flush_count[GUC_MAX_LOG_BUFFER]; >> +}; >> + >> +struct intel_guc { >> + struct intel_uc_fw fw; >> + struct intel_guc_log log; >> + struct intel_guc_ct ct; >> + >> + /* Log snapshot if GuC errors during load */ >> + struct drm_i915_gem_object *load_err_log; >> + >> + /* intel_guc_recv interrupt related state */ >> + bool interrupts_enabled; >> + >> + struct i915_vma *ads_vma; >> + struct i915_vma *stage_desc_pool; >> + void *stage_desc_pool_vaddr; >> + struct ida stage_ids; >> + >> + struct i915_guc_client *execbuf_client; >> + >> + DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); >> + uint32_t db_cacheline; /* Cyclic counter mod pagesize */ >> + >> + /* GuC's FW specific registers used in MMIO send */ >> + struct { >> + u32 base; >> + unsigned int count; >> + enum forcewake_domains fw_domains; >> + } send_regs; >> + >> + /* To serialize the intel_guc_send actions */ >> + struct mutex send_mutex; >> + >> + /* GuC's FW specific send function */ >> + int (*send)(struct intel_guc *guc, const u32 *data, u32 len); >> + >> + /* GuC's FW specific notify function */ >> + void (*notify)(struct intel_guc *guc); >> +}; >> + >> static inline int intel_guc_send(struct intel_guc *guc, >> const u32 *action, >> u32 len) >> @@ -36,6 +132,15 @@ static inline void intel_guc_notify(struct >> intel_guc *guc) >> guc->notify(guc); >> } >> +static inline u32 guc_ggtt_offset(struct i915_vma *vma) >> +{ >> + u32 offset = i915_ggtt_offset(vma); >> + >> + GEM_BUG_ON(offset < GUC_WOPCM_TOP); >> + GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, >> GUC_GGTT_TOP)); >> + return offset; >> +} >> + >> /* intel_guc.c */ >> int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 >> len); >> void intel_guc_init_early(struct intel_guc *guc); >> @@ -43,4 +148,25 @@ static inline void intel_guc_notify(struct >> intel_guc *guc) >> int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, >> u32 len); >> int intel_guc_sample_forcewake(struct intel_guc *guc); >> +/* intel_guc_loader.c */ >> +int intel_guc_select_fw(struct intel_guc *guc); >> +int intel_guc_init_hw(struct intel_guc *guc); >> +int intel_guc_suspend(struct drm_i915_private *dev_priv); >> +int intel_guc_resume(struct drm_i915_private *dev_priv); >> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv); >> + >> +/* i915_guc_submission.c */ >> +int i915_guc_submission_init(struct drm_i915_private *dev_priv); >> +int i915_guc_submission_enable(struct drm_i915_private *dev_priv); >> +void i915_guc_submission_disable(struct drm_i915_private *dev_priv); >> +void i915_guc_submission_fini(struct drm_i915_private *dev_priv); >> +struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 >> size); >> + >> +/* intel_guc_log.c */ >> +int intel_guc_log_create(struct intel_guc *guc); >> +void intel_guc_log_destroy(struct intel_guc *guc); >> +int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 >> control_val); >> +void i915_guc_log_register(struct drm_i915_private *dev_priv); >> +void i915_guc_log_unregister(struct drm_i915_private *dev_priv); >> + >> #endif >> diff --git a/drivers/gpu/drm/i915/intel_uc.h >> b/drivers/gpu/drm/i915/intel_uc.h >> index 2c11d11..30902f3 100644 >> --- a/drivers/gpu/drm/i915/intel_uc.h >> +++ b/drivers/gpu/drm/i915/intel_uc.h >> @@ -32,46 +32,6 @@ >> struct drm_i915_gem_request; >> -/* >> - * This structure primarily describes the GEM object shared with the >> GuC. >> - * The specs sometimes refer to this object as a "GuC context", but >> we use >> - * the term "client" to avoid confusion with hardware contexts. This >> - * GEM object is held for the entire lifetime of our interaction with >> - * the GuC, being allocated before the GuC is loaded with its firmware. >> - * Because there's no way to update the address used by the GuC after >> - * initialisation, the shared object must stay pinned into the GGTT as >> - * long as the GuC is in use. We also keep the first page (only) mapped >> - * into kernel address space, as it includes shared data that must be >> - * updated on every request submission. >> - * >> - * The single GEM object described here is actually made up of several >> - * separate areas, as far as the GuC is concerned. The first page (kept >> - * kmap'd) includes the "process descriptor" which holds sequence >> data for >> - * the doorbell, and one cacheline which actually *is* the doorbell; a >> - * write to this will "ring the doorbell" (i.e. send an interrupt to >> the >> - * GuC). The subsequent pages of the client object constitute the work >> - * queue (a circular array of work items), again described in the >> process >> - * descriptor. Work queue pages are mapped momentarily as required. >> - */ >> -struct i915_guc_client { >> - struct i915_vma *vma; >> - void *vaddr; >> - struct i915_gem_context *owner; >> - struct intel_guc *guc; >> - >> - uint32_t engines; /* bitmap of (host) engine ids */ >> - uint32_t priority; >> - u32 stage_id; >> - uint32_t proc_desc_offset; >> - >> - u16 doorbell_id; >> - unsigned long doorbell_offset; >> - >> - spinlock_t wq_lock; >> - /* Per-engine counts of GuC submissions */ >> - uint64_t submissions[I915_NUM_ENGINES]; >> -}; >> - >> enum intel_uc_fw_status { >> INTEL_UC_FIRMWARE_FAIL = -1, >> INTEL_UC_FIRMWARE_NONE = 0, >> @@ -138,62 +98,6 @@ struct intel_uc_fw { >> uint32_t ucode_offset; >> }; >> -struct intel_guc_log { >> - uint32_t flags; >> - struct i915_vma *vma; >> - /* The runtime stuff gets created only when GuC logging gets >> enabled */ >> - struct { >> - void *buf_addr; >> - struct workqueue_struct *flush_wq; >> - struct work_struct flush_work; >> - struct rchan *relay_chan; >> - } runtime; >> - /* logging related stats */ >> - u32 capture_miss_count; >> - u32 flush_interrupt_count; >> - u32 prev_overflow_count[GUC_MAX_LOG_BUFFER]; >> - u32 total_overflow_count[GUC_MAX_LOG_BUFFER]; >> - u32 flush_count[GUC_MAX_LOG_BUFFER]; >> -}; >> - >> -struct intel_guc { >> - struct intel_uc_fw fw; >> - struct intel_guc_log log; >> - struct intel_guc_ct ct; >> - >> - /* Log snapshot if GuC errors during load */ >> - struct drm_i915_gem_object *load_err_log; >> - >> - /* intel_guc_recv interrupt related state */ >> - bool interrupts_enabled; >> - >> - struct i915_vma *ads_vma; >> - struct i915_vma *stage_desc_pool; >> - void *stage_desc_pool_vaddr; >> - struct ida stage_ids; >> - >> - struct i915_guc_client *execbuf_client; >> - >> - DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); >> - uint32_t db_cacheline; /* Cyclic counter mod pagesize */ >> - >> - /* GuC's FW specific registers used in MMIO send */ >> - struct { >> - u32 base; >> - unsigned int count; >> - enum forcewake_domains fw_domains; >> - } send_regs; >> - >> - /* To serialize the intel_guc_send actions */ >> - struct mutex send_mutex; >> - >> - /* GuC's FW specific send function */ >> - int (*send)(struct intel_guc *guc, const u32 *data, u32 len); >> - >> - /* GuC's FW specific notify function */ >> - void (*notify)(struct intel_guc *guc); >> -}; >> - >> struct intel_huc { >> /* Generic uC firmware management */ >> struct intel_uc_fw fw; >> @@ -209,35 +113,6 @@ struct intel_huc { >> int intel_uc_init_hw(struct drm_i915_private *dev_priv); >> void intel_uc_fini_hw(struct drm_i915_private *dev_priv); >> -/* intel_guc_loader.c */ >> -int intel_guc_select_fw(struct intel_guc *guc); >> -int intel_guc_init_hw(struct intel_guc *guc); >> -int intel_guc_suspend(struct drm_i915_private *dev_priv); >> -int intel_guc_resume(struct drm_i915_private *dev_priv); >> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv); >> - >> -/* i915_guc_submission.c */ >> -int i915_guc_submission_init(struct drm_i915_private *dev_priv); >> -int i915_guc_submission_enable(struct drm_i915_private *dev_priv); >> -void i915_guc_submission_disable(struct drm_i915_private *dev_priv); >> -void i915_guc_submission_fini(struct drm_i915_private *dev_priv); >> -struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 >> size); >> - >> -/* intel_guc_log.c */ >> -int intel_guc_log_create(struct intel_guc *guc); >> -void intel_guc_log_destroy(struct intel_guc *guc); >> -int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 >> control_val); >> -void i915_guc_log_register(struct drm_i915_private *dev_priv); >> -void i915_guc_log_unregister(struct drm_i915_private *dev_priv); >> - >> -static inline u32 guc_ggtt_offset(struct i915_vma *vma) >> -{ >> - u32 offset = i915_ggtt_offset(vma); >> - GEM_BUG_ON(offset < GUC_WOPCM_TOP); >> - GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, >> GUC_GGTT_TOP)); >> - return offset; >> -} >> - >> /* intel_huc.c */ >> void intel_huc_select_fw(struct intel_huc *huc); >> void intel_huc_init_hw(struct intel_huc *huc);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5aecbf7..b0f38bb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -59,6 +59,7 @@ #include "intel_bios.h" #include "intel_dpll_mgr.h" #include "intel_uc.h" +#include "intel_guc.h" #include "intel_lrc.h" #include "intel_ringbuffer.h" diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 06f2d27..919b6e1 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -24,6 +24,102 @@ #ifndef _INTEL_GUC_H_ #define _INTEL_GUC_H_ +/* + * This structure primarily describes the GEM object shared with the GuC. + * The specs sometimes refer to this object as a "GuC context", but we use + * the term "client" to avoid confusion with hardware contexts. This + * GEM object is held for the entire lifetime of our interaction with + * the GuC, being allocated before the GuC is loaded with its firmware. + * Because there's no way to update the address used by the GuC after + * initialisation, the shared object must stay pinned into the GGTT as + * long as the GuC is in use. We also keep the first page (only) mapped + * into kernel address space, as it includes shared data that must be + * updated on every request submission. + * + * The single GEM object described here is actually made up of several + * separate areas, as far as the GuC is concerned. The first page (kept + * kmap'd) includes the "process descriptor" which holds sequence data for + * the doorbell, and one cacheline which actually *is* the doorbell; a + * write to this will "ring the doorbell" (i.e. send an interrupt to the + * GuC). The subsequent pages of the client object constitute the work + * queue (a circular array of work items), again described in the process + * descriptor. Work queue pages are mapped momentarily as required. + */ +struct i915_guc_client { + struct i915_vma *vma; + void *vaddr; + struct i915_gem_context *owner; + struct intel_guc *guc; + + uint32_t engines; /* bitmap of (host) engine ids */ + uint32_t priority; + u32 stage_id; + uint32_t proc_desc_offset; + + u16 doorbell_id; + unsigned long doorbell_offset; + + spinlock_t wq_lock; + /* Per-engine counts of GuC submissions */ + uint64_t submissions[I915_NUM_ENGINES]; +}; + +struct intel_guc_log { + uint32_t flags; + struct i915_vma *vma; + /* The runtime stuff gets created only when GuC logging gets enabled */ + struct { + void *buf_addr; + struct workqueue_struct *flush_wq; + struct work_struct flush_work; + struct rchan *relay_chan; + } runtime; + /* logging related stats */ + u32 capture_miss_count; + u32 flush_interrupt_count; + u32 prev_overflow_count[GUC_MAX_LOG_BUFFER]; + u32 total_overflow_count[GUC_MAX_LOG_BUFFER]; + u32 flush_count[GUC_MAX_LOG_BUFFER]; +}; + +struct intel_guc { + struct intel_uc_fw fw; + struct intel_guc_log log; + struct intel_guc_ct ct; + + /* Log snapshot if GuC errors during load */ + struct drm_i915_gem_object *load_err_log; + + /* intel_guc_recv interrupt related state */ + bool interrupts_enabled; + + struct i915_vma *ads_vma; + struct i915_vma *stage_desc_pool; + void *stage_desc_pool_vaddr; + struct ida stage_ids; + + struct i915_guc_client *execbuf_client; + + DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); + uint32_t db_cacheline; /* Cyclic counter mod pagesize */ + + /* GuC's FW specific registers used in MMIO send */ + struct { + u32 base; + unsigned int count; + enum forcewake_domains fw_domains; + } send_regs; + + /* To serialize the intel_guc_send actions */ + struct mutex send_mutex; + + /* GuC's FW specific send function */ + int (*send)(struct intel_guc *guc, const u32 *data, u32 len); + + /* GuC's FW specific notify function */ + void (*notify)(struct intel_guc *guc); +}; + static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) @@ -36,6 +132,15 @@ static inline void intel_guc_notify(struct intel_guc *guc) guc->notify(guc); } +static inline u32 guc_ggtt_offset(struct i915_vma *vma) +{ + u32 offset = i915_ggtt_offset(vma); + + GEM_BUG_ON(offset < GUC_WOPCM_TOP); + GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); + return offset; +} + /* intel_guc.c */ int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len); void intel_guc_init_early(struct intel_guc *guc); @@ -43,4 +148,25 @@ static inline void intel_guc_notify(struct intel_guc *guc) int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len); int intel_guc_sample_forcewake(struct intel_guc *guc); +/* intel_guc_loader.c */ +int intel_guc_select_fw(struct intel_guc *guc); +int intel_guc_init_hw(struct intel_guc *guc); +int intel_guc_suspend(struct drm_i915_private *dev_priv); +int intel_guc_resume(struct drm_i915_private *dev_priv); +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv); + +/* i915_guc_submission.c */ +int i915_guc_submission_init(struct drm_i915_private *dev_priv); +int i915_guc_submission_enable(struct drm_i915_private *dev_priv); +void i915_guc_submission_disable(struct drm_i915_private *dev_priv); +void i915_guc_submission_fini(struct drm_i915_private *dev_priv); +struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); + +/* intel_guc_log.c */ +int intel_guc_log_create(struct intel_guc *guc); +void intel_guc_log_destroy(struct intel_guc *guc); +int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val); +void i915_guc_log_register(struct drm_i915_private *dev_priv); +void i915_guc_log_unregister(struct drm_i915_private *dev_priv); + #endif diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 2c11d11..30902f3 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -32,46 +32,6 @@ struct drm_i915_gem_request; -/* - * This structure primarily describes the GEM object shared with the GuC. - * The specs sometimes refer to this object as a "GuC context", but we use - * the term "client" to avoid confusion with hardware contexts. This - * GEM object is held for the entire lifetime of our interaction with - * the GuC, being allocated before the GuC is loaded with its firmware. - * Because there's no way to update the address used by the GuC after - * initialisation, the shared object must stay pinned into the GGTT as - * long as the GuC is in use. We also keep the first page (only) mapped - * into kernel address space, as it includes shared data that must be - * updated on every request submission. - * - * The single GEM object described here is actually made up of several - * separate areas, as far as the GuC is concerned. The first page (kept - * kmap'd) includes the "process descriptor" which holds sequence data for - * the doorbell, and one cacheline which actually *is* the doorbell; a - * write to this will "ring the doorbell" (i.e. send an interrupt to the - * GuC). The subsequent pages of the client object constitute the work - * queue (a circular array of work items), again described in the process - * descriptor. Work queue pages are mapped momentarily as required. - */ -struct i915_guc_client { - struct i915_vma *vma; - void *vaddr; - struct i915_gem_context *owner; - struct intel_guc *guc; - - uint32_t engines; /* bitmap of (host) engine ids */ - uint32_t priority; - u32 stage_id; - uint32_t proc_desc_offset; - - u16 doorbell_id; - unsigned long doorbell_offset; - - spinlock_t wq_lock; - /* Per-engine counts of GuC submissions */ - uint64_t submissions[I915_NUM_ENGINES]; -}; - enum intel_uc_fw_status { INTEL_UC_FIRMWARE_FAIL = -1, INTEL_UC_FIRMWARE_NONE = 0, @@ -138,62 +98,6 @@ struct intel_uc_fw { uint32_t ucode_offset; }; -struct intel_guc_log { - uint32_t flags; - struct i915_vma *vma; - /* The runtime stuff gets created only when GuC logging gets enabled */ - struct { - void *buf_addr; - struct workqueue_struct *flush_wq; - struct work_struct flush_work; - struct rchan *relay_chan; - } runtime; - /* logging related stats */ - u32 capture_miss_count; - u32 flush_interrupt_count; - u32 prev_overflow_count[GUC_MAX_LOG_BUFFER]; - u32 total_overflow_count[GUC_MAX_LOG_BUFFER]; - u32 flush_count[GUC_MAX_LOG_BUFFER]; -}; - -struct intel_guc { - struct intel_uc_fw fw; - struct intel_guc_log log; - struct intel_guc_ct ct; - - /* Log snapshot if GuC errors during load */ - struct drm_i915_gem_object *load_err_log; - - /* intel_guc_recv interrupt related state */ - bool interrupts_enabled; - - struct i915_vma *ads_vma; - struct i915_vma *stage_desc_pool; - void *stage_desc_pool_vaddr; - struct ida stage_ids; - - struct i915_guc_client *execbuf_client; - - DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); - uint32_t db_cacheline; /* Cyclic counter mod pagesize */ - - /* GuC's FW specific registers used in MMIO send */ - struct { - u32 base; - unsigned int count; - enum forcewake_domains fw_domains; - } send_regs; - - /* To serialize the intel_guc_send actions */ - struct mutex send_mutex; - - /* GuC's FW specific send function */ - int (*send)(struct intel_guc *guc, const u32 *data, u32 len); - - /* GuC's FW specific notify function */ - void (*notify)(struct intel_guc *guc); -}; - struct intel_huc { /* Generic uC firmware management */ struct intel_uc_fw fw; @@ -209,35 +113,6 @@ struct intel_huc { int intel_uc_init_hw(struct drm_i915_private *dev_priv); void intel_uc_fini_hw(struct drm_i915_private *dev_priv); -/* intel_guc_loader.c */ -int intel_guc_select_fw(struct intel_guc *guc); -int intel_guc_init_hw(struct intel_guc *guc); -int intel_guc_suspend(struct drm_i915_private *dev_priv); -int intel_guc_resume(struct drm_i915_private *dev_priv); -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv); - -/* i915_guc_submission.c */ -int i915_guc_submission_init(struct drm_i915_private *dev_priv); -int i915_guc_submission_enable(struct drm_i915_private *dev_priv); -void i915_guc_submission_disable(struct drm_i915_private *dev_priv); -void i915_guc_submission_fini(struct drm_i915_private *dev_priv); -struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); - -/* intel_guc_log.c */ -int intel_guc_log_create(struct intel_guc *guc); -void intel_guc_log_destroy(struct intel_guc *guc); -int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val); -void i915_guc_log_register(struct drm_i915_private *dev_priv); -void i915_guc_log_unregister(struct drm_i915_private *dev_priv); - -static inline u32 guc_ggtt_offset(struct i915_vma *vma) -{ - u32 offset = i915_ggtt_offset(vma); - GEM_BUG_ON(offset < GUC_WOPCM_TOP); - GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); - return offset; -} - /* intel_huc.c */ void intel_huc_select_fw(struct intel_huc *huc); void intel_huc_init_hw(struct intel_huc *huc);
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_guc.h | 126 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_uc.h | 125 -------------------------------------- 3 files changed, 127 insertions(+), 125 deletions(-)