From patchwork Mon Sep 18 13:32:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Srinivas, Vidya" X-Patchwork-Id: 9956647 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6913960385 for ; Mon, 18 Sep 2017 13:23:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5901B28D1A for ; Mon, 18 Sep 2017 13:23:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4E14C28D28; Mon, 18 Sep 2017 13:23:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B5B7728D1A for ; Mon, 18 Sep 2017 13:23:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3DDDF6E377; Mon, 18 Sep 2017 13:23:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 586876E377 for ; Mon, 18 Sep 2017 13:23:48 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Sep 2017 06:23:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,413,1500966000"; d="scan'208";a="153080034" Received: from vsrini4-ubuntu-intel.iind.intel.com ([10.223.25.59]) by fmsmga006.fm.intel.com with ESMTP; 18 Sep 2017 06:23:45 -0700 From: Vidya Srinivas To: intel-gfx@lists.freedesktop.org Date: Mon, 18 Sep 2017 19:02:21 +0530 Message-Id: <1505741541-30907-1-git-send-email-vidya.srinivas@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505391181-9477-2-git-send-email-vidya.srinivas@intel.com> References: <1505391181-9477-2-git-send-email-vidya.srinivas@intel.com> MIME-Version: 1.0 Cc: Vidya Srinivas Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Enable scanline read for gen9 dsi X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Uma Shankar For gen9 platforms, dsi timings are driven from port instead of pipe (unlike ddi). Thus, we can't rely on pipe registers to get the timing information. Even scanline register read will not be functional. This is causing vblank evasion logic to fail since it relies on scanline, causing atomic update failure warnings. This patch uses pipe framestamp and current timestamp registers to calculate scanline. This is an indirect way to get the scanline. It helps resolve atomic update failure for gen9 dsi platforms. v2: Addressed Ville and Daniel's review comments. Updated the register MACROs, handled race condition for register reads, extracted timings from the hwmode. Removed the dependency on crtc->config to get the encoder type. v3: Made get scanline function generic Credits-to: Ville Syrjälä Signed-off-by: Uma Shankar Signed-off-by: Chandra Konduru Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_irq.c | 7 +++++ drivers/gpu/drm/i915/i915_reg.h | 11 +++++++ drivers/gpu/drm/i915/intel_display.c | 60 ++++++++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1cc31a5..d9efe83 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -4085,6 +4085,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); +u32 gen9_get_scanline(struct intel_crtc *crtc); + /* intel_dpio_phy.c */ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, enum dpio_phy *phy, enum dpio_channel *ch); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5d391e6..47668dd 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -781,6 +781,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) struct drm_vblank_crtc *vblank; enum pipe pipe = crtc->pipe; int position, vtotal; + struct intel_encoder *encoder; if (!crtc->active) return -1; @@ -792,6 +793,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) if (mode->flags & DRM_MODE_FLAG_INTERLACE) vtotal /= 2; + if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) { + for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) + if (encoder->type == INTEL_OUTPUT_DSI) + return gen9_get_scanline(crtc); + } + if (IS_GEN2(dev_priv)) position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; else diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0b03260..85168ee 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8802,6 +8802,17 @@ enum skl_power_gate { #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF +/* Gen4+ Timestamp and Pipe Frame time stamp registers */ +#define GEN4_TIMESTAMP_CTR _MMIO(MCHBAR_MIRROR_BASE + 0x2358) +#define GEN7_TIMESTAMP_CTR _MMIO(0x44070) + +#define _PIPE_FRMTMSTMP_A 0x70048 +#define _PIPE_FRMTMSTMP_B 0x71048 +#define _IVB_PIPE_FRMTMSTMP_C 0x72048 +#define PIPE_FRMTMSTMP(pipe) \ + _MMIO_PIPE3((pipe), _PIPE_FRMTMSTMP_A, \ + _PIPE_FRMTMSTMP_B, _IVB_PIPE_FRMTMSTMP_C) + /* BXT MIPI clock controls */ #define BXT_MAX_VAR_OUTPUT_KHZ 39500 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0871807..601032f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10352,6 +10352,66 @@ static bool needs_scaling(const struct intel_plane_state *state) return (src_w != dst_w || src_h != dst_h); } +/* + * For Gen9 DSI, pipe scanline register will not + * work to get the scanline since the timings + * are driven from the PORT (unlike DDI encoders). + * This function will use Framestamp and current + * timestamp registers to calculate the scanline. + */ +u32 gen9_get_scanline(struct intel_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + u32 crtc_vblank_start = crtc->base.mode.crtc_vblank_start; + u32 crtc_vtotal = crtc->base.mode.crtc_vtotal; + u32 crtc_htotal = crtc->base.mode.crtc_htotal; + u32 crtc_clock = crtc->base.mode.crtc_clock; + u64 scanline = 0, scan_prev_time, scan_curr_time, scan_post_time; + + WARN_ON(!crtc_vtotal); + if (!crtc_vtotal) + return scanline; + + /* To avoid the race condition where we might cross into the + * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR + * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR + * during the same frame. + */ + do { + /* + * This field provides read back of the display + * pipe frame time stamp. The time stamp value + * is sampled at every start of vertical blank. + */ + scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); + + /* + * The TIMESTAMP_CTR register has the current + * time stamp value. + */ + scan_curr_time = I915_READ_FW(GEN7_TIMESTAMP_CTR); + + scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); + } while (scan_post_time != scan_prev_time); + + /* + * Since the register is 32 bit and the values + * can overflow and wrap around, making sure + * current time accounts for the register + * wrap + */ + if (scan_curr_time < scan_prev_time) + scan_curr_time += 0x100000000; + + scanline = div_u64(mul_u64_u32_shr((scan_curr_time - scan_prev_time), + crtc_clock, 0), 1000 * crtc_htotal); + scanline = min(scanline, (u64)(crtc_vtotal - 1)); + scanline = (scanline + crtc_vblank_start) % crtc_vtotal; + + return scanline; +} + int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, struct drm_crtc_state *crtc_state, const struct intel_plane_state *old_plane_state,