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[93.106.162.75]) by smtp.gmail.com with ESMTPSA id g83sm22657lji.65.2017.09.19.12.44.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 12:44:15 -0700 (PDT) From: Juha-Pekka Heikkila To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Sep 2017 22:44:05 +0300 Message-Id: <1505850249-23527-2-git-send-email-juhapekka.heikkila@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505850249-23527-1-git-send-email-juhapekka.heikkila@gmail.com> References: <1505850249-23527-1-git-send-email-juhapekka.heikkila@gmail.com> Subject: [Intel-gfx] [PATCH 1/5] drm/i915: move adjusted_x/y from crtc to cache. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++ drivers/gpu/drm/i915/intel_display.c | 10 ++++++---- drivers/gpu/drm/i915/intel_drv.h | 2 -- drivers/gpu/drm/i915/intel_fbc.c | 11 ++++++++--- 4 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6d7d871..17960ba 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1095,6 +1095,14 @@ struct intel_fbc { int src_w; int src_h; bool visible; + /* + * Display surface base address adjustement for + * pageflips. Note that on gen4+ this only adjusts up + * to a tile, offsets within a tile are handled in + * the hw itself (with the TILEOFF register). + */ + int adjusted_x; + int adjusted_y; } plane; struct { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8599e42..92e8370 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3307,6 +3307,7 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, int x = plane_state->main.x; int y = plane_state->main.y; unsigned long irqflags; + struct intel_fbc *fbc = &dev_priv->fbc; linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); @@ -3315,8 +3316,8 @@ static void i9xx_update_primary_plane(struct intel_plane *primary, else crtc->dspaddr_offset = linear_offset; - crtc->adjusted_x = x; - crtc->adjusted_y = y; + fbc->state_cache.plane.adjusted_x = x; + fbc->state_cache.plane.adjusted_y = y; spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); @@ -3577,6 +3578,7 @@ static void skylake_update_primary_plane(struct intel_plane *plane, int dst_w = drm_rect_width(&plane_state->base.dst); int dst_h = drm_rect_height(&plane_state->base.dst); unsigned long irqflags; + struct intel_fbc *fbc = &dev_priv->fbc; /* Sizes are 0 based */ src_w--; @@ -3586,8 +3588,8 @@ static void skylake_update_primary_plane(struct intel_plane *plane, crtc->dspaddr_offset = surf_addr; - crtc->adjusted_x = src_x; - crtc->adjusted_y = src_y; + fbc->state_cache.plane.adjusted_x = src_x; + fbc->state_cache.plane.adjusted_y = src_y; spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3078076..62aada7 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -807,8 +807,6 @@ struct intel_crtc { * gen4+ this only adjusts up to a tile, offsets within a tile are * handled in the hw itself (with the TILEOFF register). */ u32 dspaddr_offset; - int adjusted_x; - int adjusted_y; struct intel_crtc_state *config; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 58a772d..dc059808 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) */ static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) { - return crtc->base.y - crtc->adjusted_y; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_fbc *fbc = &dev_priv->fbc; + + return crtc->base.y - fbc->state_cache.plane.adjusted_y; } /* @@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w, &effective_h); - effective_w += crtc->adjusted_x; - effective_h += crtc->adjusted_y; + effective_w += fbc->state_cache.plane.adjusted_x; + effective_h += fbc->state_cache.plane.adjusted_y; return effective_w <= max_w && effective_h <= max_h; } @@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16; cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16; cache->plane.visible = plane_state->base.visible; + cache->plane.adjusted_x = plane_state->main.x; + cache->plane.adjusted_y = plane_state->main.y; if (!cache->plane.visible) return;