From patchwork Tue Sep 19 21:25:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jim.bride@linux.intel.com X-Patchwork-Id: 9960353 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 45254601E9 for ; Tue, 19 Sep 2017 21:28:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3770C28EF6 for ; Tue, 19 Sep 2017 21:28:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2C1DB28EF8; Tue, 19 Sep 2017 21:28:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AC46028EF6 for ; Tue, 19 Sep 2017 21:28:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3A866E664; Tue, 19 Sep 2017 21:28:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id B9E9E6E664 for ; Tue, 19 Sep 2017 21:28:49 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP; 19 Sep 2017 14:28:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.42,418,1500966000"; d="scan'208"; a="1016347183" Received: from shiv.jf.intel.com ([10.54.75.141]) by orsmga003.jf.intel.com with ESMTP; 19 Sep 2017 14:28:49 -0700 From: Jim Bride To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Sep 2017 14:25:46 -0700 Message-Id: <1505856346-25845-1-git-send-email-jim.bride@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502313667-18127-1-git-send-email-jim.bride@linux.intel.com> References: <1502313667-18127-1-git-send-email-jim.bride@linux.intel.com> Cc: Paulo Zanoni , Jani Nikula , Rodrigo Vivi Subject: [Intel-gfx] [PATCH v8] drm/i915/edp: Be less aggressive about changing link config on eDP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This set of changes has some history to them. There were several attempts to add what was called "fast link training" to i915, which actually wasn't fast link training as per the DP spec. These changes were: commit 5fa836a9d859 ("drm/i915: DP link training optimization") commit 4e96c97742f4 ("drm/i915: eDP link training optimization") which were eventually hand-reverted by: commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training feature") in kernel 4.7-rc4. The eDP pieces of the above revert, however, had some very bad side-effects on PSR functionality on Skylake. The issue at hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3 (depending on the original link configuration) in order to quickly get the source and sink back in synchronization across the link before handing control back to the i915. There's an assumption that none of the link configuration information has changed (and thus it's still valid) since the last full link training operation. The revert above was identified via a bisect as the cause of some of Skylake's PSR woes. This patch, largely based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization") puts the eDP portions of this patch back in place. None of the flickering issues that spurred the revert have been seen, and I suspect the real culprits here were addressed by some of the recent link training changes that Manasi has implemented, and PSR on Skylake is definitely more happy with these changes in-place. v2 and v3: Rebase v4: * Clean up accesses to train_set_valid a bit for easier reading. (Chris) * Rebase v5: * Checkpatch cleanup * Rebase v6: * is_edp() => intel_dp_is_edp() * rebase v7: * Remove extraneous is_edp() prototype (Rodrigo) v8: Rebase Cc: Chris Wilson Cc: Rodrigo Vivi Cc: Paulo Zanoni Cc: Manasi D Navare Cc: Mika Kahola Cc: Jani Nikula Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature") Reviewed-by: Manasi Navare Signed-off-by: Jim Bride --- drivers/gpu/drm/i915/intel_dp.c | 2 ++ drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++++++++++++++- drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8db6b11..aee7e9b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4748,6 +4748,7 @@ intel_dp_long_pulse(struct intel_connector *intel_connector) intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); intel_dp->reset_link_params = false; + intel_dp->train_set_valid = false; } intel_dp_print_rates(intel_dp); @@ -6017,6 +6018,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp_set_source_rates(intel_dp); intel_dp->reset_link_params = true; + intel_dp->train_set_valid = false; intel_dp->pps_pipe = INVALID_PIPE; intel_dp->active_pipe = INVALID_PIPE; diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index 05907fa..79fe369 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -94,7 +94,8 @@ static bool intel_dp_reset_link_train(struct intel_dp *intel_dp, uint8_t dp_train_pat) { - memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); + if (!intel_dp->train_set_valid) + memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp_set_signal_levels(intel_dp); return intel_dp_set_link_train(intel_dp, dp_train_pat); } @@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE)) { DRM_ERROR("failed to enable link training\n"); + intel_dp->train_set_valid = false; return false; } + /* + * The initial set of link parameters are set by this point, so go + * ahead and set intel_dp->train_set_valid to false in case any of + * the succeeding steps fail. It will be set back to true if we were + * able to achieve clock recovery in the specified configuration. + */ + intel_dp->train_set_valid = false; + voltage_tries = 1; max_vswing_tries = 0; for (;;) { @@ -179,6 +189,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { DRM_DEBUG_KMS("clock recovery OK\n"); + intel_dp->train_set_valid = intel_dp_is_edp(intel_dp); return true; } @@ -256,6 +267,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) training_pattern | DP_LINK_SCRAMBLING_DISABLE)) { DRM_ERROR("failed to start channel equalization\n"); + intel_dp->train_set_valid = false; return false; } @@ -296,6 +308,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) /* Try 5 times, else fail and try at lower BW */ if (tries == 5) { intel_dp_dump_link_status(link_status); + intel_dp->train_set_valid = false; DRM_DEBUG_KMS("Channel equalization failed 5 times\n"); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3078076..40e98ed 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -987,6 +987,7 @@ struct intel_dp { struct drm_dp_aux aux; enum intel_display_power_domain aux_power_domain; uint8_t train_set[4]; + bool train_set_valid; int panel_power_up_delay; int panel_power_down_delay; int panel_power_cycle_delay;