From patchwork Wed Sep 20 14:32:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vathsala nagaraju X-Patchwork-Id: 9961537 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0942960208 for ; Wed, 20 Sep 2017 14:33:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EFA2C287BF for ; Wed, 20 Sep 2017 14:33:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E43DD29174; Wed, 20 Sep 2017 14:33:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD0C5287BF for ; Wed, 20 Sep 2017 14:33:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 42CCE6E748; Wed, 20 Sep 2017 14:33:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 511E66E748; Wed, 20 Sep 2017 14:33:23 +0000 (UTC) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP; 20 Sep 2017 07:33:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,421,1500966000"; d="scan'208";a="153543299" Received: from vnagaraj-hp-elitedesk-800-g1-twr.iind.intel.com ([10.223.107.109]) by fmsmga005.fm.intel.com with ESMTP; 20 Sep 2017 07:33:20 -0700 From: vathsala nagaraju To: rodrigo.vivi@intel.com, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Wed, 20 Sep 2017 20:02:35 +0530 Message-Id: <1505917955-6623-2-git-send-email-vathsala.nagaraju@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505917955-6623-1-git-send-email-vathsala.nagaraju@intel.com> References: <1505917955-6623-1-git-send-email-vathsala.nagaraju@intel.com> Cc: Puthikorn Voravootivat Subject: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3. Cc: Rodrigo Vivi CC: Puthikorn Voravootivat Signed-off-by: Vathsala Nagaraju --- drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index acb5094..04b253f 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val; + uint8_t sink_latency; val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE | - EDP_SU_TRACK_ENABLE | - EDP_FRAMES_BEFORE_SU_ENTRY; + EDP_SU_TRACK_ENABLE; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY, + &sink_latency)) { + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK; + val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT; + } else { + val |= EDP_FRAMES_BEFORE_SU_ENTRY; + } if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR2_TP2_TIME_2500;