From patchwork Wed Oct 4 14:07:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9984805 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DB7F760586 for ; Wed, 4 Oct 2017 14:04:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D05981FFAD for ; Wed, 4 Oct 2017 14:04:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C54BD205FC; Wed, 4 Oct 2017 14:04:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 576D11FFAD for ; Wed, 4 Oct 2017 14:04:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 862196E6FF; Wed, 4 Oct 2017 14:04:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 44FFA6E6FF for ; Wed, 4 Oct 2017 14:04:22 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP; 04 Oct 2017 07:04:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,477,1500966000"; d="scan'208";a="142631136" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by orsmga002.jf.intel.com with ESMTP; 04 Oct 2017 07:04:19 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Wed, 4 Oct 2017 19:37:25 +0530 Message-Id: <1507126045-24526-11-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507126045-24526-1-git-send-email-sagar.a.kamble@intel.com> References: <1507126045-24526-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH 10/10] drm/i915: Introduce separate status variable for RC6 and Ring frequency setup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Defined new struct intel_rc6 to hold RC6 specific state and intel_ring_pstate to hold ring specific state. Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 10 +++++++ drivers/gpu/drm/i915/intel_pm.c | 58 ++++++++++++++++++++++++++++++----------- 3 files changed, 54 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index c5b5a09..71349ec 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2481,7 +2481,7 @@ static int intel_runtime_suspend(struct device *kdev) struct drm_i915_private *dev_priv = to_i915(dev); int ret; - if (WARN_ON_ONCE(!(dev_priv->pm.rps.enabled && intel_rc6_enabled()))) + if (WARN_ON_ONCE(!(dev_priv->pm.rc6.enabled && intel_rc6_enabled()))) return -ENODEV; if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4d81b4c..167990c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1359,8 +1359,18 @@ struct intel_rps { struct intel_rps_ei ei; }; +struct intel_rc6 { + bool enabled; +}; + +struct intel_ring_pstate { + bool configured; +}; + struct intel_gen6_power_mgmt { struct intel_rps rps; + struct intel_rc6 rc6; + struct intel_ring_pstate ring_pstate; struct delayed_work autoenable_work; /* diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 964df7b..f0d42da 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7877,8 +7877,12 @@ static void intel_init_emon(struct drm_i915_private *dev_priv) static inline void intel_update_ring_freq(struct drm_i915_private *i915) { - if (NEEDS_RING_FREQ_UPDATE(i915)) + if (NEEDS_RING_FREQ_UPDATE(i915)) { + if (READ_ONCE(i915->pm.ring_pstate.configured)) + return; gen6_update_ring_freq(i915); + i915->pm.ring_pstate.configured = true; + } } void intel_init_gt_powersave(struct drm_i915_private *dev_priv) @@ -7971,7 +7975,8 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv) void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) { - dev_priv->pm.rps.enabled = true; /* force disabling */ + dev_priv->pm.rps.enabled = true; /* force RPS disabling */ + dev_priv->pm.rc6.enabled = true; /* force RC6 disabling */ intel_disable_gt_powersave(dev_priv); gen6_reset_rps_interrupts(dev_priv); @@ -7979,6 +7984,9 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) void intel_disable_rc6(struct drm_i915_private *dev_priv) { + if (!READ_ONCE(dev_priv->pm.rc6.enabled)) + return; + if (INTEL_GEN(dev_priv) >= 9) gen9_disable_rc6(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) @@ -7987,10 +7995,15 @@ void intel_disable_rc6(struct drm_i915_private *dev_priv) valleyview_disable_rc6(dev_priv); else if (INTEL_GEN(dev_priv) >= 6) gen6_disable_rc6(dev_priv); + + dev_priv->pm.rc6.enabled = false; } void intel_disable_rps(struct drm_i915_private *dev_priv) { + if (!READ_ONCE(dev_priv->pm.rps.enabled)) + return; + if (INTEL_GEN(dev_priv) >= 9) gen9_disable_rps(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) @@ -8001,24 +8014,30 @@ void intel_disable_rps(struct drm_i915_private *dev_priv) gen6_disable_rps(dev_priv); else if (IS_IRONLAKE_M(dev_priv)) ironlake_disable_drps(dev_priv); + + dev_priv->pm.rps.enabled = false; } void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) { - if (!READ_ONCE(dev_priv->pm.rps.enabled)) - return; - mutex_lock(&dev_priv->pm.pcu_lock); intel_disable_rc6(dev_priv); intel_disable_rps(dev_priv); + if (NEEDS_RING_FREQ_UPDATE(dev_priv)) + dev_priv->pm.ring_pstate.configured = false; - dev_priv->pm.rps.enabled = false; mutex_unlock(&dev_priv->pm.pcu_lock); } void intel_enable_rc6(struct drm_i915_private *dev_priv) { + /* We shouldn't be disabling as we submit, so this should be less + * racy than it appears! + */ + if (READ_ONCE(dev_priv->pm.rc6.enabled)) + return; + if (IS_CHERRYVIEW(dev_priv)) cherryview_enable_rc6(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) @@ -8029,10 +8048,18 @@ void intel_enable_rc6(struct drm_i915_private *dev_priv) gen8_enable_rc6(dev_priv); else if (INTEL_GEN(dev_priv) >= 6) gen6_enable_rc6(dev_priv); + + dev_priv->pm.rc6.enabled = true; } void intel_enable_rps(struct drm_i915_private *dev_priv) { + /* We shouldn't be disabling as we submit, so this should be less + * racy than it appears! + */ + if (READ_ONCE(dev_priv->pm.rps.enabled)) + return; + if (IS_CHERRYVIEW(dev_priv)) { cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { @@ -8053,16 +8080,12 @@ void intel_enable_rps(struct drm_i915_private *dev_priv) WARN_ON(dev_priv->pm.rps.efficient_freq < dev_priv->pm.rps.min_freq); WARN_ON(dev_priv->pm.rps.efficient_freq > dev_priv->pm.rps.max_freq); + + dev_priv->pm.rps.enabled = true; } void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) { - /* We shouldn't be disabling as we submit, so this should be less - * racy than it appears! - */ - if (READ_ONCE(dev_priv->pm.rps.enabled)) - return; - /* Powersaving is controlled by the host when inside a VM */ if (intel_vgpu_active(dev_priv)) return; @@ -8073,7 +8096,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) intel_enable_rps(dev_priv); intel_update_ring_freq(dev_priv); - dev_priv->pm.rps.enabled = true; mutex_unlock(&dev_priv->pm.pcu_lock); } @@ -8084,7 +8106,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work) struct intel_engine_cs *rcs; struct drm_i915_gem_request *req; - if (READ_ONCE(dev_priv->pm.rps.enabled)) + if (READ_ONCE(dev_priv->pm.rps.enabled) && + READ_ONCE(dev_priv->pm.rc6.enabled) && + !(NEEDS_RING_FREQ_UPDATE(dev_priv) ^ + READ_ONCE(dev_priv->pm.ring_pstate.configured))) goto out; rcs = dev_priv->engine[RCS]; @@ -8114,7 +8139,10 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work) void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv) { - if (READ_ONCE(dev_priv->pm.rps.enabled)) + if (READ_ONCE(dev_priv->pm.rps.enabled) && + READ_ONCE(dev_priv->pm.rc6.enabled) && + !(NEEDS_RING_FREQ_UPDATE(dev_priv) ^ + READ_ONCE(dev_priv->pm.ring_pstate.configured))) return; if (IS_IRONLAKE_M(dev_priv)) {