| Message ID | 1507126045-24526-4-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Sagar Arun Kamble (2017-10-04 15:07:18) > This patch separates enable/disable of RC6 and RPS for VLV. > > v2: Removed unnecessary comments about forcewakes while enabling > RC6/RPS. Added changes to output turbo control status for VLV in > i915_frequency_info. > > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 24 +++++++-------- > drivers/gpu/drm/i915/intel_pm.c | 61 ++++++++++++++++++++++++------------- > 2 files changed, 51 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index abb8524..17d25f9 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1041,9 +1041,19 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > seq_printf(m, "Current P-state: %d\n", > (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > - u32 freq_sts; > + u32 rpmodectl, freq_sts; > > mutex_lock(&dev_priv->rps.hw_lock); > + > + rpmodectl = I915_READ(GEN6_RP_CONTROL); > + seq_printf(m, "Video Turbo Mode: %s\n", > + yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); > + seq_printf(m, "HW control enabled: %s\n", > + yesno(rpmodectl & GEN6_RP_ENABLE)); > + seq_printf(m, "SW control enabled: %s\n", > + yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == > + GEN6_RP_MEDIA_SW_MODE)); > + > freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); > seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); > @@ -1454,21 +1464,11 @@ static void print_rc6_res(struct seq_file *m, > static int vlv_drpc_info(struct seq_file *m) > { > struct drm_i915_private *dev_priv = node_to_i915(m->private); > - u32 rpmodectl1, rcctl1, pw_status; > + u32 rcctl1, pw_status; > > pw_status = I915_READ(VLV_GTLC_PW_STATUS); > - rpmodectl1 = I915_READ(GEN6_RP_CONTROL); > rcctl1 = I915_READ(GEN6_RC_CONTROL); > > - seq_printf(m, "Video Turbo Mode: %s\n", > - yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); > - seq_printf(m, "Turbo enabled: %s\n", > - yesno(rpmodectl1 & GEN6_RP_ENABLE)); > - seq_printf(m, "HW control enabled: %s\n", > - yesno(rpmodectl1 & GEN6_RP_ENABLE)); > - seq_printf(m, "SW control enabled: %s\n", > - yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == > - GEN6_RP_MEDIA_SW_MODE)); Ok. Redundant, and this file does focus on render power control and not render power states. > seq_printf(m, "RC6 Enabled: %s\n", > yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | > GEN6_RC_CTL_EI_MODE(1)))); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 908d384..1494aa9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6342,9 +6342,9 @@ static void cherryview_disable_rps(struct drm_i915_private *dev_priv) > I915_WRITE(GEN6_RC_CONTROL, 0); > } > > -static void valleyview_disable_rps(struct drm_i915_private *dev_priv) > +static void valleyview_disable_rc6(struct drm_i915_private *dev_priv) > { > - /* we're doing forcewake before Disabling RC6, > + /* We're doing forcewake before Disabling RC6, > * This what the BIOS expects when going into suspend */ > intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > @@ -6353,6 +6353,11 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv) > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > +static void valleyview_disable_rps(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE(GEN6_RP_CONTROL, 0); > +} > + > static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode) > { > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > @@ -7278,11 +7283,11 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv) > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > -static void valleyview_enable_rps(struct drm_i915_private *dev_priv) > +static void valleyview_enable_rc6(struct drm_i915_private *dev_priv) > { > struct intel_engine_cs *engine; > enum intel_engine_id id; > - u32 gtfifodbg, val, rc6_mode = 0; > + u32 gtfifodbg, rc6_mode = 0; > > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > > @@ -7295,28 +7300,11 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) > I915_WRITE(GTFIFODBG, gtfifodbg); > } > > - /* If VLV, Forcewake all wells, else re-direct to regular path */ > intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > /* Disable RC states. */ > I915_WRITE(GEN6_RC_CONTROL, 0); > > - I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); > - I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); > - I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); > - I915_WRITE(GEN6_RP_UP_EI, 66000); > - I915_WRITE(GEN6_RP_DOWN_EI, 350000); > - > - I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); > - > - I915_WRITE(GEN6_RP_CONTROL, > - GEN6_RP_MEDIA_TURBO | > - GEN6_RP_MEDIA_HW_NORMAL_MODE | > - GEN6_RP_MEDIA_IS_GFX | > - GEN6_RP_ENABLE | > - GEN6_RP_UP_BUSY_AVG | > - GEN6_RP_DOWN_IDLE_CONT); > - > I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); > I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); > I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); > @@ -7326,7 +7314,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) > > I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); > > - /* allows RC6 residency counter to work */ > + /* Allows RC6 residency counter to work */ > I915_WRITE(VLV_COUNTER_CONTROL, > _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | > VLV_MEDIA_RC0_COUNT_EN | > @@ -7341,6 +7329,33 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) > > I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > +} > + > +static void valleyview_enable_rps(struct drm_i915_private *dev_priv) > +{ > + u32 val; > + > + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > + > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > + > + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); > + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); > + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); > + I915_WRITE(GEN6_RP_UP_EI, 66000); > + I915_WRITE(GEN6_RP_DOWN_EI, 350000); > + > + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); > + > + I915_WRITE(GEN6_RP_CONTROL, > + GEN6_RP_MEDIA_TURBO | > + GEN6_RP_MEDIA_HW_NORMAL_MODE | > + GEN6_RP_MEDIA_IS_GFX | > + GEN6_RP_ENABLE | > + GEN6_RP_UP_BUSY_AVG | > + GEN6_RP_DOWN_IDLE_CONT); > + Oh, vlv just has to be different. Poke it too hard and it bites back. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index abb8524..17d25f9 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1041,9 +1041,19 @@ static int i915_frequency_info(struct seq_file *m, void *unused) seq_printf(m, "Current P-state: %d\n", (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - u32 freq_sts; + u32 rpmodectl, freq_sts; mutex_lock(&dev_priv->rps.hw_lock); + + rpmodectl = I915_READ(GEN6_RP_CONTROL); + seq_printf(m, "Video Turbo Mode: %s\n", + yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); + seq_printf(m, "HW control enabled: %s\n", + yesno(rpmodectl & GEN6_RP_ENABLE)); + seq_printf(m, "SW control enabled: %s\n", + yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == + GEN6_RP_MEDIA_SW_MODE)); + freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); @@ -1454,21 +1464,11 @@ static void print_rc6_res(struct seq_file *m, static int vlv_drpc_info(struct seq_file *m) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - u32 rpmodectl1, rcctl1, pw_status; + u32 rcctl1, pw_status; pw_status = I915_READ(VLV_GTLC_PW_STATUS); - rpmodectl1 = I915_READ(GEN6_RP_CONTROL); rcctl1 = I915_READ(GEN6_RC_CONTROL); - seq_printf(m, "Video Turbo Mode: %s\n", - yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); - seq_printf(m, "Turbo enabled: %s\n", - yesno(rpmodectl1 & GEN6_RP_ENABLE)); - seq_printf(m, "HW control enabled: %s\n", - yesno(rpmodectl1 & GEN6_RP_ENABLE)); - seq_printf(m, "SW control enabled: %s\n", - yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == - GEN6_RP_MEDIA_SW_MODE)); seq_printf(m, "RC6 Enabled: %s\n", yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 908d384..1494aa9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6342,9 +6342,9 @@ static void cherryview_disable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC_CONTROL, 0); } -static void valleyview_disable_rps(struct drm_i915_private *dev_priv) +static void valleyview_disable_rc6(struct drm_i915_private *dev_priv) { - /* we're doing forcewake before Disabling RC6, + /* We're doing forcewake before Disabling RC6, * This what the BIOS expects when going into suspend */ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); @@ -6353,6 +6353,11 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv) intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } +static void valleyview_disable_rps(struct drm_i915_private *dev_priv) +{ + I915_WRITE(GEN6_RP_CONTROL, 0); +} + static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { @@ -7278,11 +7283,11 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv) intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } -static void valleyview_enable_rps(struct drm_i915_private *dev_priv) +static void valleyview_enable_rc6(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; enum intel_engine_id id; - u32 gtfifodbg, val, rc6_mode = 0; + u32 gtfifodbg, rc6_mode = 0; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -7295,28 +7300,11 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GTFIFODBG, gtfifodbg); } - /* If VLV, Forcewake all wells, else re-direct to regular path */ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); /* Disable RC states. */ I915_WRITE(GEN6_RC_CONTROL, 0); - I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); - I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); - I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); - I915_WRITE(GEN6_RP_UP_EI, 66000); - I915_WRITE(GEN6_RP_DOWN_EI, 350000); - - I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); - - I915_WRITE(GEN6_RP_CONTROL, - GEN6_RP_MEDIA_TURBO | - GEN6_RP_MEDIA_HW_NORMAL_MODE | - GEN6_RP_MEDIA_IS_GFX | - GEN6_RP_ENABLE | - GEN6_RP_UP_BUSY_AVG | - GEN6_RP_DOWN_IDLE_CONT); - I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); @@ -7326,7 +7314,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); - /* allows RC6 residency counter to work */ + /* Allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | VLV_MEDIA_RC0_COUNT_EN | @@ -7341,6 +7329,33 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC_CONTROL, rc6_mode); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); +} + +static void valleyview_enable_rps(struct drm_i915_private *dev_priv) +{ + u32 val; + + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); + + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); + I915_WRITE(GEN6_RP_UP_EI, 66000); + I915_WRITE(GEN6_RP_DOWN_EI, 350000); + + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); + + I915_WRITE(GEN6_RP_CONTROL, + GEN6_RP_MEDIA_TURBO | + GEN6_RP_MEDIA_HW_NORMAL_MODE | + GEN6_RP_MEDIA_IS_GFX | + GEN6_RP_ENABLE | + GEN6_RP_UP_BUSY_AVG | + GEN6_RP_DOWN_IDLE_CONT); + /* Setting Fixed Bias */ val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | @@ -7940,6 +7955,7 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) } else if (IS_CHERRYVIEW(dev_priv)) { cherryview_disable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { + valleyview_disable_rc6(dev_priv); valleyview_disable_rps(dev_priv); } else if (INTEL_GEN(dev_priv) >= 6) { gen6_disable_rc6(dev_priv); @@ -7969,6 +7985,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) if (IS_CHERRYVIEW(dev_priv)) { cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { + valleyview_enable_rc6(dev_priv); valleyview_enable_rps(dev_priv); } else if (INTEL_GEN(dev_priv) >= 9) { gen9_enable_rc6(dev_priv);