From patchwork Wed Oct 4 14:07:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9984801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9DCDB60586 for ; Wed, 4 Oct 2017 14:04:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92CFA1FFAD for ; Wed, 4 Oct 2017 14:04:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 87CBD205FC; Wed, 4 Oct 2017 14:04:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 49CEB1FFAD for ; Wed, 4 Oct 2017 14:04:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D7EB86E6FA; Wed, 4 Oct 2017 14:04:19 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19CEF6E6FA for ; Wed, 4 Oct 2017 14:04:18 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP; 04 Oct 2017 07:04:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,477,1500966000"; d="scan'208";a="142631117" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by orsmga002.jf.intel.com with ESMTP; 04 Oct 2017 07:04:15 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Wed, 4 Oct 2017 19:37:23 +0530 Message-Id: <1507126045-24526-9-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507126045-24526-1-git-send-email-sagar.a.kamble@intel.com> References: <1507126045-24526-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH 08/10] drm/i915: Create generic function to setup ring frequency table X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Prepared intel_update_ring_freq function to setup ring frequency for applicable platforms determined by macro - NEEDS_RING_FREQ_UPDATE Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg --- drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1ccc3fb..62aed72 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7868,6 +7868,19 @@ static void intel_init_emon(struct drm_i915_private *dev_priv) dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); } +#define NEEDS_RING_FREQ_UPDATE(i915) \ + (((INTEL_GEN(i915) >= 9) && \ + (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915))) || \ + (IS_BROADWELL(i915)) || \ + ((INTEL_GEN(i915) >= 6) && \ + (!IS_CHERRYVIEW(i915) && !IS_VALLEYVIEW(i915)))) + +static inline void intel_update_ring_freq(struct drm_i915_private *i915) +{ + if (NEEDS_RING_FREQ_UPDATE(i915)) + gen6_update_ring_freq(i915); +} + void intel_init_gt_powersave(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->pm.rps; @@ -8014,21 +8027,19 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) } else if (INTEL_GEN(dev_priv) >= 9) { gen9_enable_rc6(dev_priv); gen9_enable_rps(dev_priv); - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) - gen6_update_ring_freq(dev_priv); } else if (IS_BROADWELL(dev_priv)) { gen8_enable_rc6(dev_priv); gen8_enable_rps(dev_priv); - gen6_update_ring_freq(dev_priv); } else if (INTEL_GEN(dev_priv) >= 6) { gen6_enable_rc6(dev_priv); gen6_enable_rps(dev_priv); - gen6_update_ring_freq(dev_priv); } else if (IS_IRONLAKE_M(dev_priv)) { ironlake_enable_drps(dev_priv); intel_init_emon(dev_priv); } + intel_update_ring_freq(dev_priv); + WARN_ON(dev_priv->pm.rps.max_freq < dev_priv->pm.rps.min_freq); WARN_ON(dev_priv->pm.rps.idle_freq > dev_priv->pm.rps.max_freq);