diff mbox

[v2,10/11] drm/i915: Create generic functions to control RC6, RPS

Message ID 1507292020-14212-11-git-send-email-sagar.a.kamble@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sagar.a.kamble@intel.com Oct. 6, 2017, 12:13 p.m. UTC 
Prepared generic functions intel_enable_rc6, intel_disable_rc6,
intel_enable_rps and intel_disable_rps functions to setup RC6/RPS
based on platforms.

v2: Make intel_enable/disable_rc6/rps static. (Chris)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 97 ++++++++++++++++++++++++++---------------
 1 file changed, 62 insertions(+), 35 deletions(-)

Comments

Chris Wilson Oct. 6, 2017, 12:46 p.m. UTC | #1 
Quoting Sagar Arun Kamble (2017-10-06 13:13:39)
> Prepared generic functions intel_enable_rc6, intel_disable_rc6,
> intel_enable_rps and intel_disable_rps functions to setup RC6/RPS
> based on platforms.
> 
> v2: Make intel_enable/disable_rc6/rps static. (Chris)
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 97 ++++++++++++++++++++++++++---------------
>  1 file changed, 62 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ce2dc5b..03264fe 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7972,75 +7972,102 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
>         gen6_reset_rps_interrupts(dev_priv);
>  }
>  
> -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
> +static void intel_disable_rc6(struct drm_i915_private *dev_priv)
>  {
> -       if (!READ_ONCE(dev_priv->pm.rps.enabled))
> -               return;
> -
> -       mutex_lock(&dev_priv->pm.pcu_lock);

lockdep_assert_held(dev_priv->pm.pcu_lock); ?

We often skip it for statics, unless we know we are planning on adding
an interface that may not take the lock.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
sagar.a.kamble@intel.com Oct. 6, 2017, 3:02 p.m. UTC | #2 
On 10/6/2017 6:16 PM, Chris Wilson wrote:
> Quoting Sagar Arun Kamble (2017-10-06 13:13:39)
>> Prepared generic functions intel_enable_rc6, intel_disable_rc6,
>> intel_enable_rps and intel_disable_rps functions to setup RC6/RPS
>> based on platforms.
>>
>> v2: Make intel_enable/disable_rc6/rps static. (Chris)
>>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 97 ++++++++++++++++++++++++++---------------
>>   1 file changed, 62 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index ce2dc5b..03264fe 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7972,75 +7972,102 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
>>          gen6_reset_rps_interrupts(dev_priv);
>>   }
>>   
>> -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
>> +static void intel_disable_rc6(struct drm_i915_private *dev_priv)
>>   {
>> -       if (!READ_ONCE(dev_priv->pm.rps.enabled))
>> -               return;
>> -
>> -       mutex_lock(&dev_priv->pm.pcu_lock);
> lockdep_assert_held(dev_priv->pm.pcu_lock); ?
>
> We often skip it for statics, unless we know we are planning on adding
> an interface that may not take the lock.
Sure will add this. Thanks.
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ce2dc5b..03264fe 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7972,75 +7972,102 @@  void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 	gen6_reset_rps_interrupts(dev_priv);
 }
 
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+static void intel_disable_rc6(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->pm.rps.enabled))
-		return;
-
-	mutex_lock(&dev_priv->pm.pcu_lock);
-
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (INTEL_GEN(dev_priv) >= 9)
 		gen9_disable_rc6(dev_priv);
-		gen9_disable_rps(dev_priv);
-	} else if (IS_CHERRYVIEW(dev_priv)) {
+	else if (IS_CHERRYVIEW(dev_priv))
 		cherryview_disable_rc6(dev_priv);
-		cherryview_disable_rps(dev_priv);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_disable_rc6(dev_priv);
-		valleyview_disable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	else if (INTEL_GEN(dev_priv) >= 6)
 		gen6_disable_rc6(dev_priv);
+}
+
+static void intel_disable_rps(struct drm_i915_private *dev_priv)
+{
+	if (INTEL_GEN(dev_priv) >= 9)
+		gen9_disable_rps(dev_priv);
+	else if (IS_CHERRYVIEW(dev_priv))
+		cherryview_disable_rps(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
+		valleyview_disable_rps(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 6)
 		gen6_disable_rps(dev_priv);
-	}  else if (IS_IRONLAKE_M(dev_priv)) {
+	else if (IS_IRONLAKE_M(dev_priv))
 		ironlake_disable_drps(dev_priv);
-	}
-
-	dev_priv->pm.rps.enabled = false;
-	mutex_unlock(&dev_priv->pm.pcu_lock);
 }
 
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	/* We shouldn't be disabling as we submit, so this should be less
-	 * racy than it appears!
-	 */
-	if (READ_ONCE(dev_priv->pm.rps.enabled))
-		return;
-
-	/* Powersaving is controlled by the host when inside a VM */
-	if (intel_vgpu_active(dev_priv))
+	if (!READ_ONCE(dev_priv->pm.rps.enabled))
 		return;
 
 	mutex_lock(&dev_priv->pm.pcu_lock);
 
-	if (IS_CHERRYVIEW(dev_priv)) {
+	intel_disable_rc6(dev_priv);
+	intel_disable_rps(dev_priv);
+
+	dev_priv->pm.rps.enabled = false;
+	mutex_unlock(&dev_priv->pm.pcu_lock);
+}
+
+static void intel_enable_rc6(struct drm_i915_private *dev_priv)
+{
+	if (IS_CHERRYVIEW(dev_priv))
 		cherryview_enable_rc6(dev_priv);
+	else if (IS_VALLEYVIEW(dev_priv))
+		valleyview_enable_rc6(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 9)
+		gen9_enable_rc6(dev_priv);
+	else if (IS_BROADWELL(dev_priv))
+		gen8_enable_rc6(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 6)
+		gen6_enable_rc6(dev_priv);
+}
+
+static void intel_enable_rps(struct drm_i915_private *dev_priv)
+{
+	if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
-		valleyview_enable_rc6(dev_priv);
 		valleyview_enable_rps(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 9) {
-		gen9_enable_rc6(dev_priv);
 		gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
-		gen8_enable_rc6(dev_priv);
 		gen8_enable_rps(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 6) {
-		gen6_enable_rc6(dev_priv);
 		gen6_enable_rps(dev_priv);
 	} else if (IS_IRONLAKE_M(dev_priv)) {
 		ironlake_enable_drps(dev_priv);
 		intel_init_emon(dev_priv);
 	}
 
-	if (HAS_LLC(dev_priv))
-		intel_update_ring_freq(dev_priv);
-
 	WARN_ON(dev_priv->pm.rps.max_freq < dev_priv->pm.rps.min_freq);
 	WARN_ON(dev_priv->pm.rps.idle_freq > dev_priv->pm.rps.max_freq);
 
 	WARN_ON(dev_priv->pm.rps.efficient_freq < dev_priv->pm.rps.min_freq);
 	WARN_ON(dev_priv->pm.rps.efficient_freq > dev_priv->pm.rps.max_freq);
+}
+
+void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+{
+	/* We shouldn't be disabling as we submit, so this should be less
+	 * racy than it appears!
+	 */
+	if (READ_ONCE(dev_priv->pm.rps.enabled))
+		return;
+
+	/* Powersaving is controlled by the host when inside a VM */
+	if (intel_vgpu_active(dev_priv))
+		return;
+
+	mutex_lock(&dev_priv->pm.pcu_lock);
+
+	intel_enable_rc6(dev_priv);
+	intel_enable_rps(dev_priv);
+	if (HAS_LLC(dev_priv))
+		intel_update_ring_freq(dev_priv);
 
 	dev_priv->pm.rps.enabled = true;
 	mutex_unlock(&dev_priv->pm.pcu_lock);