From patchwork Fri Oct 6 12:13:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9989099 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5A49060244 for ; Fri, 6 Oct 2017 12:10:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B29828D8B for ; Fri, 6 Oct 2017 12:10:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5019C28D91; Fri, 6 Oct 2017 12:10:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E1C9528D8B for ; Fri, 6 Oct 2017 12:10:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 573436E93D; Fri, 6 Oct 2017 12:10:36 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8271A6E977 for ; Fri, 6 Oct 2017 12:10:34 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Oct 2017 05:10:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.42,483,1500966000"; d="scan'208"; a="1227803195" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by fmsmga002.fm.intel.com with ESMTP; 06 Oct 2017 05:10:32 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Fri, 6 Oct 2017 17:43:39 +0530 Message-Id: <1507292020-14212-11-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507292020-14212-1-git-send-email-sagar.a.kamble@intel.com> References: <1507292020-14212-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH v2 10/11] drm/i915: Create generic functions to control RC6, RPS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Prepared generic functions intel_enable_rc6, intel_disable_rc6, intel_enable_rps and intel_disable_rps functions to setup RC6/RPS based on platforms. v2: Make intel_enable/disable_rc6/rps static. (Chris) Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_pm.c | 97 ++++++++++++++++++++++++++--------------- 1 file changed, 62 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ce2dc5b..03264fe 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7972,75 +7972,102 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) gen6_reset_rps_interrupts(dev_priv); } -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) +static void intel_disable_rc6(struct drm_i915_private *dev_priv) { - if (!READ_ONCE(dev_priv->pm.rps.enabled)) - return; - - mutex_lock(&dev_priv->pm.pcu_lock); - - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 9) gen9_disable_rc6(dev_priv); - gen9_disable_rps(dev_priv); - } else if (IS_CHERRYVIEW(dev_priv)) { + else if (IS_CHERRYVIEW(dev_priv)) cherryview_disable_rc6(dev_priv); - cherryview_disable_rps(dev_priv); - } else if (IS_VALLEYVIEW(dev_priv)) { + else if (IS_VALLEYVIEW(dev_priv)) valleyview_disable_rc6(dev_priv); - valleyview_disable_rps(dev_priv); - } else if (INTEL_GEN(dev_priv) >= 6) { + else if (INTEL_GEN(dev_priv) >= 6) gen6_disable_rc6(dev_priv); +} + +static void intel_disable_rps(struct drm_i915_private *dev_priv) +{ + if (INTEL_GEN(dev_priv) >= 9) + gen9_disable_rps(dev_priv); + else if (IS_CHERRYVIEW(dev_priv)) + cherryview_disable_rps(dev_priv); + else if (IS_VALLEYVIEW(dev_priv)) + valleyview_disable_rps(dev_priv); + else if (INTEL_GEN(dev_priv) >= 6) gen6_disable_rps(dev_priv); - } else if (IS_IRONLAKE_M(dev_priv)) { + else if (IS_IRONLAKE_M(dev_priv)) ironlake_disable_drps(dev_priv); - } - - dev_priv->pm.rps.enabled = false; - mutex_unlock(&dev_priv->pm.pcu_lock); } -void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) +void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) { - /* We shouldn't be disabling as we submit, so this should be less - * racy than it appears! - */ - if (READ_ONCE(dev_priv->pm.rps.enabled)) - return; - - /* Powersaving is controlled by the host when inside a VM */ - if (intel_vgpu_active(dev_priv)) + if (!READ_ONCE(dev_priv->pm.rps.enabled)) return; mutex_lock(&dev_priv->pm.pcu_lock); - if (IS_CHERRYVIEW(dev_priv)) { + intel_disable_rc6(dev_priv); + intel_disable_rps(dev_priv); + + dev_priv->pm.rps.enabled = false; + mutex_unlock(&dev_priv->pm.pcu_lock); +} + +static void intel_enable_rc6(struct drm_i915_private *dev_priv) +{ + if (IS_CHERRYVIEW(dev_priv)) cherryview_enable_rc6(dev_priv); + else if (IS_VALLEYVIEW(dev_priv)) + valleyview_enable_rc6(dev_priv); + else if (INTEL_GEN(dev_priv) >= 9) + gen9_enable_rc6(dev_priv); + else if (IS_BROADWELL(dev_priv)) + gen8_enable_rc6(dev_priv); + else if (INTEL_GEN(dev_priv) >= 6) + gen6_enable_rc6(dev_priv); +} + +static void intel_enable_rps(struct drm_i915_private *dev_priv) +{ + if (IS_CHERRYVIEW(dev_priv)) { cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { - valleyview_enable_rc6(dev_priv); valleyview_enable_rps(dev_priv); } else if (INTEL_GEN(dev_priv) >= 9) { - gen9_enable_rc6(dev_priv); gen9_enable_rps(dev_priv); } else if (IS_BROADWELL(dev_priv)) { - gen8_enable_rc6(dev_priv); gen8_enable_rps(dev_priv); } else if (INTEL_GEN(dev_priv) >= 6) { - gen6_enable_rc6(dev_priv); gen6_enable_rps(dev_priv); } else if (IS_IRONLAKE_M(dev_priv)) { ironlake_enable_drps(dev_priv); intel_init_emon(dev_priv); } - if (HAS_LLC(dev_priv)) - intel_update_ring_freq(dev_priv); - WARN_ON(dev_priv->pm.rps.max_freq < dev_priv->pm.rps.min_freq); WARN_ON(dev_priv->pm.rps.idle_freq > dev_priv->pm.rps.max_freq); WARN_ON(dev_priv->pm.rps.efficient_freq < dev_priv->pm.rps.min_freq); WARN_ON(dev_priv->pm.rps.efficient_freq > dev_priv->pm.rps.max_freq); +} + +void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) +{ + /* We shouldn't be disabling as we submit, so this should be less + * racy than it appears! + */ + if (READ_ONCE(dev_priv->pm.rps.enabled)) + return; + + /* Powersaving is controlled by the host when inside a VM */ + if (intel_vgpu_active(dev_priv)) + return; + + mutex_lock(&dev_priv->pm.pcu_lock); + + intel_enable_rc6(dev_priv); + intel_enable_rps(dev_priv); + if (HAS_LLC(dev_priv)) + intel_update_ring_freq(dev_priv); dev_priv->pm.rps.enabled = true; mutex_unlock(&dev_priv->pm.pcu_lock);