From patchwork Sat Oct 7 07:07:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9991217 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D4FE760244 for ; Sat, 7 Oct 2017 07:04:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7C9B21327 for ; Sat, 7 Oct 2017 07:04:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BCE6826E75; Sat, 7 Oct 2017 07:04:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4B6A421327 for ; Sat, 7 Oct 2017 07:04:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E4986EA48; Sat, 7 Oct 2017 07:04:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0FF976EA42 for ; Sat, 7 Oct 2017 07:04:32 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2017 00:04:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.42,487,1500966000"; d="scan'208"; a="1203240957" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by fmsmga001.fm.intel.com with ESMTP; 07 Oct 2017 00:04:30 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Sat, 7 Oct 2017 12:37:34 +0530 Message-Id: <1507360055-19948-12-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507360055-19948-1-git-send-email-sagar.a.kamble@intel.com> References: <1507360055-19948-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH v3 11/12] drm/i915: Create generic functions to control RC6, RPS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Prepared generic functions intel_enable_rc6, intel_disable_rc6, intel_enable_rps and intel_disable_rps functions to setup RC6/RPS based on platforms. v2: Make intel_enable/disable_rc6/rps static. (Chris) v3: Added lockdep_assert_held(dev_priv->pcu_lock) in new generic functions. (Chris) Removed WARN_ON(&dev_priv->pcu_lock) from lower level functions as generic function now has lockdep_assert. Rebase. Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg Reviewed-by: Chris Wilson #2 Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_pm.c | 116 ++++++++++++++++++++++++---------------- 1 file changed, 70 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c4aa50f..f125d5f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6729,8 +6729,6 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) int rc6_mode; int ret; - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock)); - I915_WRITE(GEN6_RC_STATE, 0); /* Clear the DBG now so we don't confuse earlier errors */ @@ -6803,8 +6801,6 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) static void gen6_enable_rps(struct drm_i915_private *dev_priv) { - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock)); - /* Here begins a magic sequence of register writes to enable * auto-downclocking. * @@ -7225,8 +7221,6 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv) enum intel_engine_id id; u32 gtfifodbg, rc6_mode = 0, pcbr; - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock)); - gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV | GT_FIFO_FREE_ENTRIES_CHV); if (gtfifodbg) { @@ -7279,8 +7273,6 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv) { u32 val; - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock)); - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); /* 1: Program defaults and thresholds for RPS*/ @@ -7325,8 +7317,6 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv) enum intel_engine_id id; u32 gtfifodbg, rc6_mode = 0; - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock)); - valleyview_check_pctx(dev_priv); gtfifodbg = I915_READ(GTFIFODBG); @@ -7372,8 +7362,6 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) { u32 val; - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock)); - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); @@ -7987,31 +7975,47 @@ static inline void intel_disable_llc_pstate(struct drm_i915_private *i915) /* Currently there is no HW configuration to be done to disable. */ } -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) +static void intel_disable_rc6(struct drm_i915_private *dev_priv) { - struct intel_rps *rps = &dev_priv->gt_pm.rps; + lockdep_assert_held(&dev_priv->pcu_lock); - if (!READ_ONCE(rps->enabled)) - return; + if (INTEL_GEN(dev_priv) >= 9) + gen9_disable_rc6(dev_priv); + else if (IS_CHERRYVIEW(dev_priv)) + cherryview_disable_rc6(dev_priv); + else if (IS_VALLEYVIEW(dev_priv)) + valleyview_disable_rc6(dev_priv); + else if (INTEL_GEN(dev_priv) >= 6) + gen6_disable_rc6(dev_priv); +} - mutex_lock(&dev_priv->pcu_lock); +static void intel_disable_rps(struct drm_i915_private *dev_priv) +{ + lockdep_assert_held(&dev_priv->pcu_lock); - if (INTEL_GEN(dev_priv) >= 9) { - gen9_disable_rc6(dev_priv); + if (INTEL_GEN(dev_priv) >= 9) gen9_disable_rps(dev_priv); - } else if (IS_CHERRYVIEW(dev_priv)) { - cherryview_disable_rc6(dev_priv); + else if (IS_CHERRYVIEW(dev_priv)) cherryview_disable_rps(dev_priv); - } else if (IS_VALLEYVIEW(dev_priv)) { - valleyview_disable_rc6(dev_priv); + else if (IS_VALLEYVIEW(dev_priv)) valleyview_disable_rps(dev_priv); - } else if (INTEL_GEN(dev_priv) >= 6) { - gen6_disable_rc6(dev_priv); + else if (INTEL_GEN(dev_priv) >= 6) gen6_disable_rps(dev_priv); - } else if (IS_IRONLAKE_M(dev_priv)) { + else if (IS_IRONLAKE_M(dev_priv)) ironlake_disable_drps(dev_priv); - } +} + +void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) +{ + struct intel_rps *rps = &dev_priv->gt_pm.rps; + if (!READ_ONCE(rps->enabled)) + return; + + mutex_lock(&dev_priv->pcu_lock); + + intel_disable_rc6(dev_priv); + intel_disable_rps(dev_priv); if (HAS_LLC(dev_priv)) intel_disable_llc_pstate(dev_priv); @@ -8026,50 +8030,70 @@ static inline void intel_enable_llc_pstate(struct drm_i915_private *i915) gen6_update_ring_freq(i915); } -void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) +static void intel_enable_rc6(struct drm_i915_private *dev_priv) { - struct intel_rps *rps = &dev_priv->gt_pm.rps; + lockdep_assert_held(&dev_priv->pcu_lock); - /* We shouldn't be disabling as we submit, so this should be less - * racy than it appears! - */ - if (READ_ONCE(rps->enabled)) - return; + if (IS_CHERRYVIEW(dev_priv)) + cherryview_enable_rc6(dev_priv); + else if (IS_VALLEYVIEW(dev_priv)) + valleyview_enable_rc6(dev_priv); + else if (INTEL_GEN(dev_priv) >= 9) + gen9_enable_rc6(dev_priv); + else if (IS_BROADWELL(dev_priv)) + gen8_enable_rc6(dev_priv); + else if (INTEL_GEN(dev_priv) >= 6) + gen6_enable_rc6(dev_priv); +} - /* Powersaving is controlled by the host when inside a VM */ - if (intel_vgpu_active(dev_priv)) - return; +static void intel_enable_rps(struct drm_i915_private *dev_priv) +{ + struct intel_rps *rps = &dev_priv->gt_pm.rps; - mutex_lock(&dev_priv->pcu_lock); + lockdep_assert_held(&dev_priv->pcu_lock); if (IS_CHERRYVIEW(dev_priv)) { - cherryview_enable_rc6(dev_priv); cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { - valleyview_enable_rc6(dev_priv); valleyview_enable_rps(dev_priv); } else if (INTEL_GEN(dev_priv) >= 9) { - gen9_enable_rc6(dev_priv); gen9_enable_rps(dev_priv); } else if (IS_BROADWELL(dev_priv)) { - gen8_enable_rc6(dev_priv); gen8_enable_rps(dev_priv); } else if (INTEL_GEN(dev_priv) >= 6) { - gen6_enable_rc6(dev_priv); gen6_enable_rps(dev_priv); } else if (IS_IRONLAKE_M(dev_priv)) { ironlake_enable_drps(dev_priv); intel_init_emon(dev_priv); } - if (HAS_LLC(dev_priv)) - intel_enable_llc_pstate(dev_priv); - WARN_ON(rps->max_freq < rps->min_freq); WARN_ON(rps->idle_freq > rps->max_freq); WARN_ON(rps->efficient_freq < rps->min_freq); WARN_ON(rps->efficient_freq > rps->max_freq); +} + +void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) +{ + struct intel_rps *rps = &dev_priv->gt_pm.rps; + + /* We shouldn't be disabling as we submit, so this should be less + * racy than it appears! + */ + if (READ_ONCE(rps->enabled)) + return; + + /* Powersaving is controlled by the host when inside a VM */ + if (intel_vgpu_active(dev_priv)) + return; + + mutex_lock(&dev_priv->pcu_lock); + + intel_enable_rc6(dev_priv); + intel_enable_rps(dev_priv); + if (HAS_LLC(dev_priv)) + intel_enable_llc_pstate(dev_priv); rps->enabled = true; mutex_unlock(&dev_priv->pcu_lock);