From patchwork Tue Oct 10 12:17:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Srinivas X-Patchwork-Id: 9995959 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D745360216 for ; Tue, 10 Oct 2017 12:09:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA78626E3C for ; Tue, 10 Oct 2017 12:09:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BDB9D2858E; Tue, 10 Oct 2017 12:09:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0AE1E26E3C for ; Tue, 10 Oct 2017 12:09:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DD816E43A; Tue, 10 Oct 2017 12:09:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 930046E43A for ; Tue, 10 Oct 2017 12:09:50 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Oct 2017 05:09:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.42,504,1500966000"; d="scan'208"; a="1023630245" Received: from vsrini4-ubuntu-intel.iind.intel.com ([10.223.25.59]) by orsmga003.jf.intel.com with ESMTP; 10 Oct 2017 05:09:48 -0700 From: Vidya Srinivas To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Oct 2017 17:47:51 +0530 Message-Id: <1507637878-17165-8-git-send-email-vidya.srinivas@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507637878-17165-1-git-send-email-vidya.srinivas@intel.com> References: <1507637878-17165-1-git-send-email-vidya.srinivas@intel.com> Subject: [Intel-gfx] [PATCH 07/14] drm/i915/skl+: make sure higher latency level has higher wm value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Mahesh Kumar DDB allocation optimization algorithm require/assumes ddb allocation for any memory C-state level DDB value to be as high as level below. Render decompression require level WM to be as high as wm level-0. This patch fulfils both the requirements. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e931e4a..c99639b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4499,6 +4499,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, uint16_t ddb_allocation, int level, const struct skl_wm_params *wp, + const struct skl_wm_level *result_prev, struct skl_wm_level *result /* out */) { const struct drm_plane_state *pstate = &intel_pstate->base; @@ -4564,6 +4565,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, } else { res_blocks++; } + + /* + * Make sure result blocks for higher latency levels are atleast + * as high as level below. + * Assumption in DDB algorithm optimization for special cases. + * Also covers Display WA #1125 for RC. + */ + if (result_prev->plane_res_b > res_blocks) + res_blocks = result_prev->plane_res_b; } if (res_blocks >= ddb_allocation || res_lines > 31) { @@ -4622,6 +4632,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, for (level = 0; level <= max_level; level++) { struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] : &wm->wm[level]; + struct skl_wm_level *result_prev; + + if (level) + result_prev = plane_num ? &wm->uv_wm[level - 1] : + &wm->wm[level - 1]; + else + result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0]; ret = skl_compute_plane_wm(dev_priv, cstate, @@ -4629,6 +4646,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, ddb_blocks, level, wm_params, + result_prev, result); if (ret) return ret;