From patchwork Wed Oct 11 08:54:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9999065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 29C89602BF for ; Wed, 11 Oct 2017 08:51:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A7D128964 for ; Wed, 11 Oct 2017 08:51:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0F80728970; Wed, 11 Oct 2017 08:51:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9AE8D28964 for ; Wed, 11 Oct 2017 08:51:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CC1F46E602; Wed, 11 Oct 2017 08:51:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id ECBFB6E600 for ; Wed, 11 Oct 2017 08:51:39 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2017 01:51:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.43,360,1503385200"; d="scan'208"; a="1204581624" Received: from sakamble-desktop.iind.intel.com ([10.223.26.118]) by fmsmga001.fm.intel.com with ESMTP; 11 Oct 2017 01:51:37 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Oct 2017 14:24:14 +0530 Message-Id: <1507712056-25030-20-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507712056-25030-1-git-send-email-sagar.a.kamble@intel.com> References: <1507712056-25030-1-git-send-email-sagar.a.kamble@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v13 19/21] drm/i915/guc: Fix enable/disable of GuC GGTT invalidate functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP i915_ggtt_enable_guc has to happen first during i915_gem_resume if GuC loading is enabled before GTT restore. In case GuC is not loaded this enabling happening during intel_uc_init_hw need to skipped. (avoid the GEM_BUG_ON) i915_ggtt_disable_guc at the end of reset/suspend/unload is needed post GGTT suspend operations. Calling it during uc_sanitize covers all scenarios. Hence, it is removed from intel_uc_fini_hw. Also these needto be protected by struct_mutex. Hence struct_mutex locking is added in i915_gem_sanitize while sanitizing uC. struct_mutex is already held during i915_gem_reset_prepare. Signed-off-by: Sagar Arun Kamble Cc: Michal Wajdeczko Cc: Michał Winiarski Cc: Chris Wilson Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 4 ++++ drivers/gpu/drm/i915/intel_uc.c | 16 +++++++++++----- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a4bbf6c..77a0746 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4759,6 +4759,10 @@ void i915_gem_resume(struct drm_i915_private *dev_priv) WARN_ON(dev_priv->gt.awake); mutex_lock(&dev->struct_mutex); + /* We need to notify the guc whenever we change the GGTT */ + if (i915_modparams.enable_guc_loading) + i915_ggtt_enable_guc(dev_priv); + i915_gem_restore_gtt_mappings(dev_priv); i915_gem_restore_fences(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 9010ab5..0b799fe 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -184,8 +184,14 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) guc_disable_communication(guc); gen9_reset_guc_interrupts(dev_priv); - /* We need to notify the guc whenever we change the GGTT */ - i915_ggtt_enable_guc(dev_priv); + /* + * We need to notify the guc whenever we change the GGTT. + * During resume from sleep we would have already updated the + * GGTT invalidate function for GuC during i915_gem_resume so + * we need to skip here. Will enable here on driver load/reset. + */ + if (!guc->suspended) + i915_ggtt_enable_guc(dev_priv); if (i915_modparams.enable_guc_submission) { /* @@ -309,9 +315,6 @@ void intel_uc_cleanup(struct drm_i915_private *dev_priv) guc_free_load_err_log(guc); i915_guc_submission_cleanup(dev_priv); - - if (i915_modparams.enable_guc_loading) - i915_ggtt_disable_guc(dev_priv); } /** @@ -452,6 +455,9 @@ void intel_uc_sanitize(struct drm_i915_private *dev_priv) struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; if (i915_modparams.enable_guc_loading) { + if (guc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS) + i915_ggtt_disable_guc(dev_priv); + guc_fw->load_status = INTEL_UC_FIRMWARE_NONE; huc_fw->load_status = INTEL_UC_FIRMWARE_NONE; }