diff mbox

[v3,14/22] drm/i915/cfl: Move GT and Display workarounds from init_clock_gating

Message ID 1507928056-6966-15-git-send-email-oscar.mateo@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

oscar.mateo@intel.com Oct. 13, 2017, 8:54 p.m. UTC 
To their rightful place inside intel_workarounds.c

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c          | 23 +----------------------
 drivers/gpu/drm/i915/intel_workarounds.c |  9 +++++++++
 2 files changed, 10 insertions(+), 22 deletions(-)

Comments

Chris Wilson Oct. 17, 2017, 12:54 p.m. UTC | #1 
Quoting Oscar Mateo (2017-10-13 21:54:08)
> To their rightful place inside intel_workarounds.c
> 
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef74251..f1f2023 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8453,25 +8453,6 @@  static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
-static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-	if (!HAS_PCH_CNP(dev_priv))
-		return;
-
-	/* Wa #1181 */
-	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
-		   CNP_PWM_CGE_GATING_DISABLE);
-}
-
-static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-	cnp_init_clock_gating(dev_priv);
-
-	/* WaFbcNukeOnHostModify:cfl */
-	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
-}
-
 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* WaDisableSDEUnitClockGating:kbl */
@@ -8948,10 +8929,8 @@  static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_CANNONLAKE(dev_priv))
+	if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 		dev_priv->display.init_clock_gating = nop_init_clock_gating;
-	else if (IS_COFFEELAKE(dev_priv))
-		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
 	else if (IS_SKYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = skl_init_clock_gating;
 	else if (IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 682ac13..63086ef 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -907,6 +907,15 @@  static int cfl_display_workarounds_init(struct drm_i915_private *dev_priv)
 	if (ret)
 		return ret;
 
+	if (HAS_PCH_CNP(dev_priv)) {
+		/* Wa #1181 */
+		DISPLAY_WA_SET_BIT(SOUTH_DSPCLK_GATE_D,
+				   CNP_PWM_CGE_GATING_DISABLE);
+	}
+
+	/* WaFbcNukeOnHostModify:cfl */
+	DISPLAY_WA_SET_BIT(ILK_DPFC_CHICKEN, ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+
 	return 0;
 }