From patchwork Wed Oct 25 23:08:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10027315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6647260245 for ; Wed, 25 Oct 2017 23:08:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5965628C79 for ; Wed, 25 Oct 2017 23:08:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4DCF528C7D; Wed, 25 Oct 2017 23:08:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F271D28C79 for ; Wed, 25 Oct 2017 23:08:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CE7C6E33C; Wed, 25 Oct 2017 23:08:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 534706E319 for ; Wed, 25 Oct 2017 23:08:24 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2017 16:08:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,433,1503385200"; d="scan'208";a="913793143" Received: from relo-linux-1.fm.intel.com ([10.1.27.112]) by FMSMGA003.fm.intel.com with ESMTP; 25 Oct 2017 16:08:20 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Wed, 25 Oct 2017 16:08:05 -0700 Message-Id: <1508972891-35322-3-git-send-email-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508972891-35322-1-git-send-email-daniele.ceraolospurio@intel.com> References: <1508972891-35322-1-git-send-email-daniele.ceraolospurio@intel.com> Subject: [Intel-gfx] [PATCH i-g-t v2 2/8] lib/igt_gt: add intel_measure_ring_size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The logic to measure the ring size is replicated almost identically in several tests. Adding it as a common function will make the code cleaner. The tests are updated in follow up patches. Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson --- lib/igt_gt.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/igt_gt.h | 2 ++ 2 files changed, 85 insertions(+) diff --git a/lib/igt_gt.c b/lib/igt_gt.c index 89727d2..76fdbc5 100644 --- a/lib/igt_gt.c +++ b/lib/igt_gt.c @@ -40,6 +40,7 @@ #include "ioctl_wrappers.h" #include "intel_reg.h" #include "intel_chipset.h" +#include "igt_dummyload.h" /** * SECTION:igt_gt @@ -577,6 +578,88 @@ unsigned intel_detect_and_clear_missed_interrupts(int fd) return missed; } +static void alarm_handler(int sig) +{ +} + +/** + * intel_measure_ring_size: + * @fd: open i915 drm file descriptor + * @engine: execbuf engine flag + * @new_ctx: use a new context to account for the space used by the lrc init + * + * This function calculates the maximum number of batches that can be inserted + * at the same time in the ring on the selected engine. + * + * Returns: + * Number of batches that fit in the ring + */ +unsigned int intel_measure_ring_size(int fd, unsigned int engine, bool new_ctx) +{ + struct sigaction old_sa, sa = { .sa_handler = alarm_handler }; + struct drm_i915_gem_exec_object2 obj[2]; + struct drm_i915_gem_execbuffer2 execbuf; + const uint32_t bbe = MI_BATCH_BUFFER_END; + unsigned int count, last; + struct itimerval itv; + struct igt_cork cork; + + igt_require_intel(fd); + + memset(obj, 0, sizeof(obj)); + obj[1].handle = gem_create(fd, 4096); + gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe)); + + memset(&execbuf, 0, sizeof(execbuf)); + execbuf.buffers_ptr = to_user_pointer(&obj[1]); + execbuf.buffer_count = 1; + execbuf.flags = engine; + gem_execbuf(fd, &execbuf); + gem_sync(fd, obj[1].handle); + + obj[0].handle = igt_cork_plug(fd, &cork); + + execbuf.buffers_ptr = to_user_pointer(obj); + execbuf.buffer_count = 2; + + if (new_ctx) + execbuf.rsvd1 = gem_context_create(fd); + + sigaction(SIGALRM, &sa, &old_sa); + itv.it_interval.tv_sec = 0; + itv.it_interval.tv_usec = 100; + itv.it_value.tv_sec = 0; + itv.it_value.tv_usec = 1000; + setitimer(ITIMER_REAL, &itv, NULL); + + last = -1; + count = 0; + do { + if (ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf) == 0) { + count++; + continue; + } + + if (last == count) + break; + + last = count; + } while (1); + + memset(&itv, 0, sizeof(itv)); + setitimer(ITIMER_REAL, &itv, NULL); + sigaction(SIGALRM, &old_sa, NULL); + + igt_cork_unplug(&cork); + gem_close(fd, obj[0].handle); + gem_close(fd, obj[1].handle); + + if (new_ctx) + gem_context_destroy(fd, execbuf.rsvd1); + + return count; +} + const struct intel_execution_engine intel_execution_engines[] = { { "default", NULL, 0, 0 }, { "render", "rcs0", I915_EXEC_RENDER, 0 }, diff --git a/lib/igt_gt.h b/lib/igt_gt.h index 2579cbd..4e4fc01 100644 --- a/lib/igt_gt.h +++ b/lib/igt_gt.h @@ -63,6 +63,8 @@ void igt_clflush_range(void *addr, int size); unsigned intel_detect_and_clear_missed_interrupts(int fd); +unsigned int intel_measure_ring_size(int fd, unsigned int engine, bool new_ctx); + extern const struct intel_execution_engine { const char *name; const char *full_name;